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realtek RTD2553V series RTD2553V series flat panel display controller fully technology preliminary revision version 1.0 last updated: 2005/11/04 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 2 overview realtek RTD2553V series products are all-in-one lcd monitor controllers supporting uxga/wsxga+/wxga+/sxga(optional), and integrate realtek high performance adc, tmds rx(optional), scaling engine, osd engine, lvds tx, rsds tx and so on. moreover, all products are pin compatible in qfp128-pin package to save cost and make the design easier .the RTD2553V series derivative pin compatible products are listed below by application: part number adc dvi hdcp resolution output package RTD2553V 210mhz (2 ports) yes no wuxga/uxga/ wsxga+ lvds/rsds/ttl 128 qfp rtd2533v 165mhz (2 ports) yes no sxga/wxga+ lvds/rsds/ttl 128 qfp rtd2033v 165mhz (2 ports) no no sxga/wxga+ lvds/rsds/ttl 128 qfp RTD2553Vh 210mhz (2 ports) yes yes wuxga/uxga/ wsxga+ lvds/rsds/ttl 128 qfp rtd2533vh 165mhz (2 ports) yes yes sxga/wxga+ lvds/rsds/ttl 128 qfp note: the following datasheet will take RTD2553V as an example and if it exists any optional feature not supported in all RTD2553V series products, we will mark optional after it. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 3 1. features............................................................................................................................................5 2. architecture...............................................................................................................................18 3. functional description........................................................................................................19 3.1 input.................................................................................................................................................19 digital input (itu 656)....................................................................................................................................................19 digital video 16-bit input................................................................................................................................................21 analog input....................................................................................................................................................................22 tmds input.....................................................................................................................................................................22 input capture window.....................................................................................................................................................23 3.2 output timing..................................................................................................................................24 display output timing....................................................................................................................................................24 display active window...................................................................................................................................................27 3.3 color processing..............................................................................................................................28 3.4 osd & color lut..........................................................................................................................28 build-in osd...................................................................................................................................................................28 color lut & overlay port..............................................................................................................................................28 3.5 auto-adjustment..............................................................................................................................29 auto-position...................................................................................................................................................................29 auto-tracking..................................................................................................................................................................29 3.6 pll system......................................................................................................................................29 dclk pll......................................................................................................................................................................29 m2pll.............................................................................................................................................................................30 adc pixel sampling pll...............................................................................................................................................30 3.7 host interface...................................................................................................................................31 parallel/serial port determination:..................................................................................................................................31 host interface location determination:..........................................................................................................................31 double data rate serial/parallel interface:.....................................................................................................................32 3.8 reset output....................................................................................................................................33 3.9 the programmable schmitt trigger of hsync..............................................................................34 3.10 crystal frequency output..............................................................................................................34 4. register description..............................................................................................................35 global event flag....................................................................................................................................35 input video capture...............................................................................................................................38 input frame window.............................................................................................................................42 fifo window........................................................................................................................................45 digital filter...........................................................................................................................................45 scaling up function..............................................................................................................................47 fifo frequency.....................................................................................................................................51 scaling down control...........................................................................................................................52 peaking filter and coring control...........................................................................................................55 display format......................................................................................................................................56 frame sync fine tune...........................................................................................................................61 display fine tune..................................................................................................................................62 sync processor.......................................................................................................................................63 macro vision..........................................................................................................................................70 highlight window..................................................................................................................................71 color processor control.........................................................................................................................75 brightness coefficient:..........................................................................................................................76 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 4 gamma control......................................................................................................................................78 dithering control...................................................................................................................................79 overlay/color palette/background color control................................................................................81 image auto function.............................................................................................................................82 video (color space conversion)...........................................................................................................86 embedded timing controller................................................................................................................88 rsds display data bus control...........................................................................................................91 tcon horizontal/vertical timing setting............................................................................................91 dot masking...........................................................................................................................................94 control for lvds..................................................................................................................................96 pin share...............................................................................................................................................100 embedded osd...................................................................................................................................104 reset out and panel switch mos control..........................................................................................104 schmitt trigger control.......................................................................................................................105 phase-lock-loop (pll)......................................................................................................................107 adc pll1...........................................................................................................................................110 adc pll2...........................................................................................................................................111 display pll.....................................................................................................................................114 multiply pll for input cyrstal..........................................................................................116 pll test............................................................................................................................................118 dclk spread spectrum......................................................................................................................119 embedded tmds................................................................................................................................122 hdcp...................................................................................................................................................132 watch dog...........................................................................................................................................140 embedded adc...................................................................................................................................141 icm......................................................................................................................................................147 dcc.....................................................................................................................................................149 cyclic-redundant-check.....................................................................................................................154 ddc special function access (ddc/ci)............................................................................................156 ddc channel (adc/dvi)..................................................................................................................159 embedded osd...................................................................................................................................161 5.electric specification.........................................................................................................203 dc characteristics...............................................................................................................................203 6. mechanical specification.................................................................................................204 7. ordering information.........................................................................................................206 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 5 1. features general l embedded dual ddc with ddc1/2b/ci l zoom scaling up and down l no external memory required. l require only one crystal to generate all timing. l programmable 3.3v/5v detection reset output. l embedded crystal output to micro-controller. l 3 channels 8 bits pwm output, and wide range selectable pwm frequency. analog rgb input interface l integrated 8-bit triple-channel 210/165 (optional) mhz adc/pll l embedded programmable schmitt trigger of hsync l support sync on green (sog) and various kinds of composite sync modes l on-chip high-performance hybrid plls l high resolution true 64 phase adc pll l y/pb/pr support up to hdtv 1080i resolution l support 2/1 analog input (optional) digital video input interface l support 8-bit video (itu 656) format input l support 16-bit video (itu 601) format input (optional) l built-in yuv to rgb color space converter & de-interlace dvi compliant digital input interface (optional) l single link on-chip tmds receiver l long cable 25m support to 165mhz l adaptive algorithm for tmds capability l data enable only mode support l high-bandwidth digital content protection (hdcp 1.1) (optional only in h version) l enhanced protection of hdcp secret key (optional only in h version) auto detection /auto calibration l input format detection l compatibility with standard vesa mode and support user-defined mode l smart engine for phase/image position/color calibration scaling l fully programmable zoom ratios l independent horizontal/vertical scaling l advanced zoom algorithm provides high image quality l sharpness/smooth filter enhancement l support non-linear scaling from 4:3 to 16:9 or 16:9 to 4:3 vivid color ? l dynamic contrast control (dcc) l independent color management (icm) l true 10 bits color processing engine l srgb compliance l advanced dithering logic for 18-bit panel color depth enhancement l dynamic overshoot-smear canceling engine l brightness and contrast control l programmable 10-bit gamma support output interface l fully programmable display timing generator l flexible data pair swapping for easier system design. l programmable tcon function support l multi-output interface (rsds/lvds/ttl)on single pcb l spread-spectrum dpll to reduce emi l fixed last line output for perfect panel capability host interface l support mcu serial/parallel bus interface. l support mcu dual edge data latch. embedded osd l embedded 12k sram dynamically stores osd command and fonts l support multi-color ram font, 1, 2 and 4-bit per pixel l 16 color palette with 24bit true color selection l maximum 8 window with alpha-blending/ gradient/dynamic fade-in/fade-out, bordering/ shadow/3d window type l rotary 90,180,270 degree l independent row shadowing/bordering l programmable blinking effects for each character l osd-made internal pattern generator for factory mode l support 12x18~4x18 proportional font l decompress osd font power & technology l 3.3v power supplier l 0.18um cmos process, 128-pin qfp package l embedded 3.3v to 1.8v voltage regulator l embedded 3.3v mos panel switch http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 6 RTD2553V 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 txec- nc nc nc nc nc n c n c nc nc 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 0 3 1 0 4 txe2+ nc txe3+ txe3- txec+ txe2- txe1+ txoc- txo2+ txe1- pvcc pgnd txe0+ txe0- txo3+ txo3- txoc+ txo2- nc 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 s d i o [ 1 ] / v 8 _ 2 b j t _ b nc nc s c l k / v 1 6 _ y 0 s d i o [ 1 ] / v 1 6 _ y 4 v c c k g n d k d d c s d a 1 d d c s c l 1 s c l k / v 8 _ 6 s c s b / v 8 _ 5 adc_vdd ahs0 a h s 1 / v 8 _ 0 / v 1 6 _ c 0 a v s 1 / v c l k nc txo1+ txo1- nc nc txo0+ txo0- nc p w m 0 c o u t r e s e t _ o u t nc n c n c n c n c 3 3 v p n l o u t v c c k g n d k d d c s c l 2 / v c l k rx2p/rx0p avs0 rxcn rxcp tmds_gnd rx2n/rx0n rx0p/rx2p tmds_vdd rx1n rx1p tmds_gnd rx0n/rx2n rext tmds_tst/pwm0 pll_test2/pwm1 s d i o [ 2 ] / v 8 _ 3 s d i o [ 3 ] / v 8 _ 4 x o b0- adc_gnd sog0 r0+ r1+/ v8_1/ v16_c1 adc_vdd g0- g0+ b0+ adc_gnd p v c c p g n d n c n c s d i o [ 2 ] / v 1 6 _ y 3 s d i o [ 0 ] / v 1 6 _ y 5 d d c s d a 2 / v 8 _ 7 v 8 _ 0 / p w m 1 b1+/ v8_6/ v16_c6 g1-/ v8_5/ v16_c5 g1+/ v8_4/ v16_c4 sog1/ v8_3/ v16_c3 v 1 6 _ d e n v 1 6 _ h s r1-/ v8_2/ v16_c2 r0- b1-/ v8_7/ v16_c7 t c o n 7 pll_test1/pwm0 apll_vdd apll_gnd n c 3 3 v r s t _ r e f n c x i p g n d s c s b / v 1 6 _ y 1 p v c c s d i o [ 0 ] / v 8 _ 1 s d i o [ 3 ] / v 1 6 _ y 2 p w m 1 / c o u t / v 1 6 _ y 7 p w m 2 / v 1 6 _ y 6 tmds_vdd v 1 6 _ o d d v 1 6 _ v s 2a/video+1d with lvds optional (tmds, video16, adc port1) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 7 RTD2553V 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bg1n/ tcon0 b j t _ b nc bg3p/ tcon5 bclkn/ tcon6 bclkp/ tcon7 b b 2 p / t c o n 1 1 b b 2 n / t c o n 1 0 bg3n/ tcon4 nc 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 0 3 1 0 4 br3p/ 0 bg2p/ tcon3 bg2n/ tcon2 bg1p/ tcon1 br3n/ 0 br2p/ 0 ab2n/ tcon10 ab1p/ tcon9 br2n/ 0 pvcc pgnd br1p/ 0 br1n/ 0 ab3p/ tcon13 ab3n/ tcon12 ab2p/ tcon11 ab1n/tcon8 ar3p/ 0 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 s d i o [ 1 ] / v 8 _ 2 / t c o n 8 p g n d nc nc p v c c s c l k / t c o n 3 / v 1 6 _ y 0 s d i o [ 1 ] / t c o n 7 / v 1 6 _ y 4 v c c k g n d k d d c s d a 1 / t c o n 9 d d c s c l 1 / t c o n 4 s c l k / v 8 _ 6 / t c o n 3 s c s b / v 8 _ 5 / t c o n 7 ahs0 avs0 adc_gnd t c o n 1 1 / v 1 6 _ o d d ag1n / tcon0 aclkp/ tcon7 aclkn/ tcon6 ag2p/ tcon3 ag2n/ tcon2 ag3p/ tcon5 ag3n/ tcon4 ag1p/ tcon1 t c o n 9 / p w m 0 v c c k r e s e t _ o u t ar3n/ 0 a r 2 p / 0 a r 2 n / 0 a r 1 p / 0 a r 1 n / 0 3 3 v p n l o u t g n d k t c o n 1 3 / c o u t d d c s c l 2 / v c l k / t c o n 4 tmds_vdd rxcn rxcp tmds_gnd rx0n rx0p tmds_vdd rx1n rx1p tmds_gnd rx0n/rx2n rx0p/rx2p rext tmds_tst/pwm0/tcon2 pll_test2/tcon1/tcon12/pwm1 s d i o [ 2 ] / v 8 _ 3 / t c o n 5 s d i o [ 3 ] / v 8 _ 4 / t c o n 9 x o b0+ r1-/v8_2/v16_c2 b0- g0- r1+/v8_1/v16_c1 adc_vdd g0+ sog0 t c o n 5 / t c o n 1 0 / v 1 6 _ d e n adc_gnd adc_vdd b b 3 p / t c o n 1 3 b b 3 n / t c o n 1 2 bb1p/ tcon9 bb1n/ tcon8 s d i o [ 2 ] / t c o n 1 1 / v 1 6 _ y 3 s d i o [ 0 ] / t c o n 1 3 / v 1 6 _ y 5 d d c s d a 2 / v 8 _ 7 / t c o n 6 / t c o n 1 1 v 8 _ 0 / p w m 1 / t c o n 2 / t c o n 7 p w m 1 / t c o n 0 / c o u t / v 1 6 _ y 7 b1+/v8_6/ v16_c6 b1-/v8_7/ v16_c7 g1+/v8_4/v16_c4 g1-/v8_5/v16_c5 a h s 1 / v 8 _ 0 / v 1 6 _ c 0 a v s 1 / v c l k sog1/v8_3/v16_c3 r0+ r0- p w m 2 / t c o n 1 / t c o n 7 / v 1 6 _ y 6 pll_test1/tcon0/tcon3/pwm0 apll_vdd apll_gnd n c 3 3 v r s t _ r e f n c x i p g n d s c s b / t c o n 1 2 / v 1 6 _ y 1 p v c c s d i o [ 0 ] / v 8 _ 1 / t c o n 1 0 s d i o [ 3 ] / t c o n 0 / v 1 6 _ y 2 t c o n 4 / t c o n 8 / v 1 6 _ h s t c o n 7 t c o n 3 / t c o n 9 / v 1 6 _ v s 2a/video+1d with 6-bit single/dual-port rsds + tcon http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 8 RTD2553V 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 br2n/ tcon0 b j t _ b bg0p/ ab3p bg1n/ tcon4 bg1p/ tcon5 bg3p/ tcon9 bg3n/ tcon8 bg0n/ ab3n 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 0 3 1 0 4 br1p/ 0 br3p/ tcon3 br3n/ tcon2 br2p/ tcon1 br1n/ 0 br0p/ 0 ab1n/ tcon10 ab0p/ tcon9 br0n/ 0 pvcc pgnd 0 0 ab2p/ tcon13 ab2n/ tcon12 ab1p/ tcon11 ab0n/tcon8 ag0p/ tcon1 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 a r 0 p / v 8 _ 0 / t c o n 2 / t c o n 7 p g n d p v c c b b 0 n / t c o n 1 2 b b 2 n / s d i o [ 3 ] / t c o n 0 / v 1 6 _ y 2 v c c k g n d k d d c s d a 1 / t c o n 9 d d c s c l 1 / t c o n 4 s c l k / v 8 _ 6 / t c o n 3 s c s b / v 8 _ 5 / t c o n 7 ahs0 avs0 adc_gnd t c o n 1 1 ag1n/ tcon2 aclkp/ tcon7 aclkn/ tcon6 ag2p/ 0 ag2n/ 0 ag3p/ tcon5 ag3n/ tcon4 ag1p/ tcon3 t c o n 9 / p w m 0 v c c k r e s e t _ o u t ag0n/ tcon0 ar3p/ 0 ar3n/ 0 a r 2 p / 0 a r 2 n / 0 3 3 v p n l o u t g n d k t c o n 1 3 / c o u t d d c s c l 2 / v c l k / t c o n 4 tmds_vdd rxcn rxcp tmds_gnd rx0n rx0p tmds_vdd rx1n rx1p tmds_gnd rx0n/rx2n rx0p/rx2p rext tmds_tst/pwm0/tcon2 pll_test2/tcon1/tcon12/pwm1 a r 0 n / s d i o [ 0 ] / v 8 _ 1 / t c o n 1 0 s d i o [ 3 ] / v 8 _ 4 / t c o n 9 x o b0+ r1-/v8_2/ v16_c2 b0- g0- r1+/ v8_1/ v16_c1 adc_vdd g0+ sog0 t c o n 5 / t c o n 1 0 adc_gnd adc_vdd b c l k p / t c o n 1 1 b c l k n / t c o n 1 0 bg2p/ tcon7 bg2n/ tcon6 b b 1 p / s c s b / t c o n 1 2 / v 1 6 _ y 1 b b 2 p / s d i o [ 2 ] / t c o n 1 1 / v 1 6 _ y 3 d d c s d a 2 / v 8 _ 7 / t c o n 6 / t c o n 1 1 a r 1 p / 0 b b 3 p / s d i o [ 0 ] / t c o n 1 3 / v 1 6 _ y 5 b1+/ v8_6/ v16_c6 b1-/ v8_7/ v16_c7 g1+/ v8_4/ v16_c4 g1-/v8_5/ v16_c5 a h s 1 / v 8 _ 0 / v 1 6 _ c 0 a v s 1 / v c l k sog1/v8_3/ v16_3 r0+ r0- b b 3 n / s d i o [ 1 ] / t c o n 7 / v 1 6 _ y 4 pll_test1/tcon0/tcon3/pwm0 apll_vdd apll_gnd n c 3 3 v r s t _ r e f n c x i p g n d b b 0 p / t c o n 1 3 p v c c a r 1 n / 0 b b 1 n / s c l k / t c o n 3 / v 1 6 _ y 0 t c o n 4 / t c o n 8 t c o n 7 t c o n 3 / t c o n 9 s d i o [ 2 ] / v 8 _ 3 / t c o n 5 s d i o [ 1 ] / v 8 _ 2 / t c o n 8 p w m 2 / t c o n 1 / t c o n 7 / v 1 6 _ y 6 p w m 1 / t c o n 0 / c o u t / v 1 6 _ y 7 2a/video+1d with 8-bit single rsds + tcon http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 9 RTD2553V 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 br2n b j t _ b bg0p bg1n bg1p bg3p bg3n bg0n 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 0 3 1 0 4 br1p br3p br3n br2p br1n br0p ab1n ab0p br0n pvcc pgnd ab3p ab3n ab2p ab2n ab1p ab0n ag0p 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 a r 0 p p g n d p v c c b b 0 n b b 2 n v c c k g n d k d d c s d a 1 / t c o n 9 d d c s c l 1 / t c o n 4 s c l k s c s b ahs0 avs0 adc_gnd t c o n 1 1 ag1n aclkp aclkn ag2p ag2n ag3p ag3n ag1p t c o n 9 / p w m 0 v c c k r e s e t _ o u t ag0n ar3p ar3n a r 2 p a r 2 n 3 3 v p n l o u t g n d k t c o n 1 3 / c o u t d d c s c l 2 / t c o n 4 tmds_vdd rxcn rxcp tmds_gnd rx0n rx0p tmds_vdd rx1n rx1p tmds_gnd rx0n/rx2n rx0p/rx2p rext tmds_tst/pwm0/tcon2 pll_test2/tcon1/tcon12/pwm 1 a r 0 n s d i o [ 3 ] x o b0+ r1-/v8_2 b0- g0- r1+/v8_1 adc_vdd g0+ sog0 t c o n 5 / t c o n 1 0 adc_gnd adc_vdd b c l k p b c l k n bg2p bg2n b b 1 p b b 2 p d d c s d a 2 / t c o n 6 / t c o n 1 1 a r 1 p b b 3 p b1+/v8_6 b1-/v8_7 g1+/v8_4 g1-/v8_5 a h s 1 / v 8 _ 0 a v s 1 / v c l k sog1/v8_3 r0+ r0- b b 3 n pll_test1/tcon0/tcon3/pwm 0 apll_vdd apll_gnd n c 3 3 v r s t _ r e f n c x i p g n d b b 0 p p v c c a r 1 n b b 1 n t c o n 4 / t c o n 8 t c o n 7 t c o n 3 / t c o n 9 t c o n 5 t c o n 8 p w m 2 / t c o n 1 / t c o n 7 p w m 1 / t c o n 0 / c o u t 2a +1d with 8-bit dual rsds + tcon http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 10 RTD2553V 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bred2/ 0 t c o n 3 / t c o n 9 / v 1 6 _ v s nc bgrn7/ tcon5 nc/ tcon6 bclk/ tcon7 b b l u 5 / t c o n 1 1 b b l u 4 / t c o n 1 0 bgrn6/ tcon4 nc 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 0 3 1 0 4 bred7/ 0 b j t _ b bgrn5/ tcon3 bgrn4/ tcon2 bred3/ 0 bred6/ 0 bred5/ 0 ablu4/tcon10 ablu3/ tcon9 bred4/ 0 pvcc pgnd bgrn3/ tcon1 bgrn2/ tcon0 ablu7/ tcon13 ablu6/ tcon12 ablu5/ tcon11 ablu2/ tcon8 ared7/ 0 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 s d i o [ 1 ] / v 8 _ 2 / t c o n 8 p g n d nc nc p v c c s c l k / t c o n 3 / v 1 6 _ y 0 s d i o [ 1 ] / t c o n 7 / d e n a / v 1 6 _ y 4 v c c k g n d k d d c s d a 1 / t c o n 9 d d c s c l 1 / t c o n 4 s c l k / v 8 _ 6 / t c o n 3 s c s b / v 8 _ 5 / t c o n 7 ahs0 avs0 adc_gnd adc_vdd agrn2/ tcon0 aclk/ tcon7 nc/ tcon6 agrn5/tcon3 agrn4/ tcon2 agrn7/ tcon5 agrn6/ tcon4 agrn3/ tcon1 v c c k 3 3 v p n l o u t g n d k ared6/ 0 a r e d 5 / 0 a r e d 4 / 0 a r e d 3 / 0 a r e d 2 / 0 t c o n 9 / p w m 0 r e s e t _ o u t t c o n 1 3 / c o u t d d c s c l 2 / v c l k / t c o n 4 / d e n a tmds_vdd rxcn rxcp tmds_gnd rx0n rx0p tmds_vdd rx1n rx1p tmds_gnd rx2n rx2p rext tmds_tst/pwm0/tcon2 pll_test2/tcon1/tcon12/dhs/pwm1 s d i o [ 2 ] / v 8 _ 3 / t c o n 5 s d i o [ 3 ] / v 8 _ 4 / t c o n 9 x o b0+ r1-/ v8_2/ v16_c2 b0- g0- r1+/ v8_1/ v16_c1 t c o n 7 g0+ sog0 p w m 2 / t c o n 1 / t c o n 7 / d v s / v 1 6 _ y 6 adc_gnd adc_vdd b b l u 7 / t c o n 1 3 b b l u 6 / t c o n 1 2 bblu3/ tcon9 bblu2/ tcon8 s d i o [ 2 ] / t c o n 1 1 / d h s / v 1 6 _ y 3 s d i o [ 0 ] / t c o n 1 3 / v 1 6 _ y 5 d d c s d a 2 / v 8 _ 7 / t c o n 6 / t c o n 1 1 v 8 _ 0 / t c o n 2 / t c o n 7 p w m 1 / t c o n 0 / d h s / c o u t / v 1 6 _ y 7 b1+/ v8_6/ v16_c6 b1-/ v8_7/ v16_c7 g1+/ v8_4/ v16_c4 g1-/ v8_5/ v16_c5 a v s 1 / v c l k a h s 1 / v 8 _ 0 / v 1 6 _ c 0 sog1/ v8_3/ v16_c3 r0+ r0- t c o n 5 / t c o n 1 0 / v 1 6 _ d e n pll_test1/tcon0/tcon3/dvs/pwm0 apll_vdd apll_gnd n c 3 3 v r s t _ r e f n c x i p g n d s c s b / t c o n 1 2 / v 1 6 _ y 1 p v c c s d i o [ 0 ] / v 8 _ 1 / t c o n 1 0 s d i o [ 3 ] / t c o n 0 / v 1 6 _ y 2 t c o n 1 1 / v 1 6 _ o d d t c o n 4 / t c o n 8 / v 1 6 _ h s 2a/video+1d with 6-bit single/dual-port ttl http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 11 RTD2553V 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bred2/ 0 b j t _ b nc bgrn7/ tcon5 bblu0/ tcon6 bblu1/tcon7 b b l u 5 / t c o n 1 1 b b l u 4 / t c o n 1 0 bgrn6/ tcon4 nc 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 1 0 3 1 0 4 bgrn3/ tcon1 t c o n 3 / t c o n 9 bgrn5/ tcon3 bgrn4/ tcon2 bred3/ 0 bgrn2/ tcon0 bred7/ 0 ablu4/ tcon10 ablu3/ tcon9 bred6/ 0 pvcc pgnd bred5/ 0 bred4/ 0 ablu7/ tcon13 ablu6/ tcon12 ablu5/ tcon11 ablu2/ tcon8 ared7/ 0 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 a g r n 1 p g n d nc nc p v c c b g r n 1 d e n a / t c o n 7 v c c k g n d k d d c s d a 1 / t c o n 9 d d c s c l 1 / t c o n 4 s c l k s c s b ahs0 avs0 adc_gnd adc_vdd agrn2/ tcon0 ablu1/ tcon7 ablu0/ tcon6 agrn5/ tcon3 agrn4/ tcon2 agrn7/ tcon5 agrn6/ tcon4 agrn3/ tcon1 v c c k 3 3 v p n l o u t g n d k ared6/ 0 a r e d 5 / 0 a r e d 4 / 0 a r e d 3 / 0 a r e d 2 / 0 3 3 v r s t _ r e f r e s e t _ o u t t c o n 1 3 / c o u t d d c s c l 2 / d e n a / t c o n 4 tmds_vdd rxcn rxcp tmds_gnd rx0n rx0p tmds_vdd rx1n rx1p tmds_gnd rx2n rx2p rext tmds_tst/ tcon2/ pwm0 pll_test2/ dhs/ tcon1/ tcon12/ pwm1 a g r n 0 s d i o [ 3 ] x o b0+ r1-/ v8_2 b0- g0- r1+/ v8_1 t c o n 7 g0+ sog0 t c o n 5 / t c o n 1 0 adc_gnd adc_vdd b b l u 7 / t c o n 1 3 b b l u 6 / t c o n 1 2 bblu3/ tcon9 bblu2/ tcon8 b g r n 0 d c l k / t c o n 1 3 d d c s d a 2 / d c l k / t c o n 6 / t c o n 1 1 a r e d 1 d h s / t c o n 0 / p w m 1 / c o u t b1-/ v8_7 b1+/ v8_6 g1+/ v8_4 g1-/ v8_5 a h s 1 / v 8 _ 0 a v s 1 / v c l k sog1/ v8_3 r0+ r0- d v s / t c o n 1 / t c o n 7 / p w m 2 pll_test1/ dvs/ tcon0/ tcon3/ pwm0 apll_vdd apll_gnd n c t c o n 9 / p w m 0 n c x i p g n d b r e d 0 p v c c a r e d 0 b r e d 1 t c o n 1 1 t c o n 4 / t c o n 8 2a+1d with 8-bit single/dual-port ttl http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 12 (i/o legend: a = analog, i = input, o = output, p = power, g = ground) n input port name i/o no description note adc_gnd ag 22 adc ground adc_gnd ag 37 adc ground b0+ ai 23 1 st positive blue analog input (pb+) b0- ai 24 1 st negative blue analog input (pb-) sog0 ai 25 1 st sync on green g0+ ai 26 1 st positive green analog input (y+) g0- ai 27 1 st negative green analog input (y-) r0+ ai 28 1 st positive red analog input (pr+) r0- ai 29 1 st negative red analog input (pr-) adc_vdd ap 21 adc power (1.8v) adc_vdd ap 38 adc power (1.8v) b1+/v8_6 ai/i 31 2 nd positive blue analog input (pb+)/ video8_6 3.3 tolerance b1-/v8_7 ai/i 30 2 nd positive blue analog input (pb-)/ video8_7 3.3 tolerance sog1/v8_3 ai/i 34 2 nd sync on green /video8_3 3.3 tolerance g1+/v8_4 ai/i 33 2 nd positive green analog input (y+)/ video8_4 3.3 tolerance g1-/v8_5 ai/i 32 2 nd negative green analog input (y-)/ video8_5 3.3 tolerance r1+/v8_1 ai/i 36 2 nd positive red analog input (pr+)/ video8_1 3.3 tolerance r1-/v8_2 ai/i 35 2 nd negative red analog input (pr-)/ video8_2 3.3 tolerance avs0 i 19 1 st adc vertical sync input power from pin 13 no power 5v tolerance ahs0 i 20 1 st adc horizontal sync input adjustable schmidt trigger power from pin 13 no power 5v tolerance ahs1/v8_0 i 39 2 nd adc horizontal sync input/video8_0 adjustable schmidt trigger power from pin 59 no power 5v tolerance avs1/vclk i 40 2 nd adc vertical sync input /video clock power from pin 59 no power 5v tolerance n pll name i/o pin no description note xo ao 127 crystal osc output xi ai 128 reference clock input from external crystal or from single-ended cmos/ttl osc 3.3v tolerance apll_vdd ap 2 power for multi-phase pll 3.3v pll_test1 i/o 3 test pin 1 power-on-latch for mcu crystal location pll_test2 i/o 4 test pin 2 m2pll apll_gnd ag 1 ground for multi-phase pll n host interface name i/o pin no description note sdio[0] i/o 52/112 parallel port data [0] (open drain)lsb 5v tolerance sdio[1] i/o 53/113 parallel port data [1] (open drain) 5v tolerance http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 13 sdio[2] i/o 54/114 parallel port data [2] (open drain) 5v tolerance sdio[3] i/o 55/115 serial control i/f data in or parallel port data [3] (open drain) msb 5v tolerance scsb i 56/118 serial control i/f chip select 5v tolerance sclk i 57/119 serial control i/f clock 5v tolerance n tmds (optional) name i/o pin no description note tmds_tst aio 5 tmds_test pin power-on-latch for host interface type rext ai 6 impedance match reference. tmds_vdd ap 7 tmds power (3.3v) rx2p ai 8 differential data input rx2n ai 9 differential data input tmds_gnd ag 10 tmds ground rx1p ai 11 differential data input rx1n ai 12 differential data input tmds_vdd ap 13 tmds power (3.3v) rx0p ai 14 differential data input rx0n ai 15 differential data input tmds_gnd ag 16 tmds ground rxcp ai 17 differential data input rxcn ai 18 differential data input n video 8 name i/o pin no description v8_0 ~ v8_7 i 111~115, 118~120/ 39, 36~30 video 8 data input vclk i 121/ 40 video8 clock input n video 16 (optional) name i/o pin no description v16_y0 ~ v16_y7 i 57~52, 49, 48/ 39, 36~30 video16 y data v16_c0 ~ v16_c0 i 39, 36~30/ 57~52, 49, 48/ video16 c data vclk i 40 video16 clock v16_den i 42 video16 data enable v16_odd i 43 video16 odd v16_hs i 44 video16 hs v16_vs i 45 video16 vs n pad/digital power & ground name i/o pin no description pad 3.3v power p 59/72/83/ 95/108 pvcc pad 3.3v ground g 60/71/84/ 96/107 pgnd digital 1.8v power p 47/116 vcck digital 1.8v ground g 46/117 gndk n lvds display interface name i/o no description http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 14 txe3+ o 73 txe3- o 74 txec+ o 75 txec- o 76 txe2+ o 77 txe2- o 78 txe1+ o 79 txe1- o 80 txe0+ o 81 txe0- o 82 txo3+ o 85 txo3- o 86 txoc+ o 87 txoc- o 88 txo2+ o 89 txo2- o 90 txo1+ o 91 txo1- o 92 txo0+ o 93 txo0- o 94 n 6-bit rsds display interface name i/o no description bb3p o 61 bb3n o 62 bb2p o 63 bb2n o 64 bb1p o 65 bb1n o 66 bclkp o 67 bclkn o 68 bg3p o 69 bg3n o 70 bg2p o 73 bg2n o 74 bg1p o 75 bg1n o 76 br3p o 77 br3n o 78 br2p o 79 br2n o 80 br1p o 81 br1n o 82 ab3p o 85 ab3n o 86 ab2p o 87 ab2n o 88 ab1p o 89 ab1n o 90 aclkp o 91 aclkn o 92 ag3p o 93 ag3n o 94 ag2p o 97 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 15 ag2n o 98 ag1p o 99 ag1n o 100 ar3p o 101 ar3n o 102 ar2p o 103 ar2n o 104 ar1p o 105 ar1n o 106 n ttl 8/6 bits interface name i/o no description bblu7 o 61 bblu6 o 62 bblu5 o 63 bblu4 o 64 bblu3 o 65 bblu2 o 66 bblu1/nc o 67 bblu0/nc o 68 bgrn7 o 69 bgrn6 o 70 bgrn5 o 73 bgrn4 o 74 bgrn3 o 75 bgrn2 o 76 bgrn1/nc o 55 bgrn0/nc o 54 bred7 o 77 bred6 o 78 bred5 o 79 bred4 o 80 bred3 o 81 bred2 o 82 bred1/nc o 57 bred0/bclk o 56 ablu7 o 85 ablu6 o 86 ablu5 o 87 ablu4 o 88 ablu3 o 89 ablu2 o 90 ablu1/aclk o 91 ablu0/nc o 92 agrn7 o 93 agrn6 o 94 agrn5 o 97 agrn4 o 98 agrn3 o 99 agrn2 o 100 agrn1/nc o 113 agrn0/nc o 114 ared7 o 101 ared6 o 102 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 16 ared5 o 103 ared4 o 104 ared3 o 105 ared2 o 106 ared1/nc o 111 ared0/nc o 112 n timing controller name i/o no description tcon0 o 3/55/48/76/100 refer to pin share part. tcon1 o 4/49/75/99 tcon2 o 5/74/98/111 tcon3 o 3/45/57/73/97/ 119 tcon4 o 44/50/70/94/ 121 tcon5 o 42/ 69/93/114 tcon6 o 68/92/120 tcon7 o 49/53/67/91/ 118 /41/111 tcon8 o 44 /66/90/113 tcon9 o 45/ 51/65/89/ 115/122 tcon10 o 42 /64/88/112 tcon11 o 43/ 54/63/87 /120 tcon12 o 4/56/62/86 tcon13 o 52/61/85/110 n ddc channel name i/o no description ddcscl1(adc) i 50 open drain, no power 5v tolerance ddcsda1(adc) i/o 51 open drain, no power 5v tolerance ddcscl2(dvi) (optional) i 121 / 113 open drain, no power 5v tolerance ddcsda2(dvi) (optional) i/o 120 / 114 open drain, no power 5v tolerance n pwm name i/o no description pwm0 o 3/5/122 pwm1 o 4/48/111 pwm2 o 49/112 n misc name i/o no description reset_out o 123 reset out open drain (internal 75kohm high), 5v tolerance cout o 110/48 crystal out 33vrst_ref i 124 reference 3.3v for reset out 33vpnlout o 109 panel on/off switch out (max current driving 1a) bjt_b o 58 embedded regulator p type bjt control pin out n crystal out pin out decision table http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 17 host interface mcu location crystal pin out parallel left 110 or 48 serial left 110 or 48 parallel right 110 or 48 serial right 110 or 48 the cout can be output from pin48 or pin110, dependent on power on latch pin 3. power on latch pins: tmds_tst(pin 5) C host interface selection (1 for parallel, 0 for serial) pll_test1(pin 3) C rtd host interface location & cout selection (1 for 112-115,118/119, 110, 0 for 52-57, 48) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 18 2. architecture rtd video decoder y pb pr d v i r g b mcu rsds/lvds/ttl panel p a n e l v c c c v b s 5 to 3.3 regulator 5v power source r g b reset figure 1 mcu rtd rst cout http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 19 3. functional description 3.1 input digital input (itu 656) rtd is designed to connect the interface of digital signal from video decoder. input data is latched within a capture window defined in registers. the timing scheme designed for input devices are showed in the following diagram. there are not h sync v sync signals provided by the video decoder with itu bt.656, these synchronal signals have to be generated by decoding the eav & sav timing reference signals. xxxu0y0v0y1u2 vgbclk vgb_r(byte) figure 2 input yuv 4:2:2(8-bits) timing only 254 of possible 256 8-bit words may be used to express a signal value, 0 and 255 are reserved for data identification purposes. video 8 data stream is as below: blanking period timing reference code 720 pixels yuv 422 data timing reference code blanking period 80 10 ff 00 00 sav cb0 y0 cr0 y1 cb2 y2 $ cr718 y719 ff 00 00 eav 80 10 $ cbn: u(b-y) colour difference component yn : luminance component crn: v(r-y) colour difference component sav/eav format bit 7 bit 6(f) bit 5(v) bit 4(h) bit 3(p3) bit 2(p2) bit 1(p1) bit 0(p0) 1 field bit 1 st field f=0 2 nd field f=1 vertical blanking bit v=1 active video v=0 h=0 in sav h=1 in eav protection bits http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 20 hardware can recognize the occurrence of eav & sav by detecting the 0xff , 0x00 , 0x00 data sequence, and then generate the hsync vsync field signals internally by decoding the fourth word of the timing reference signal(eav sav). f & v change state synchronously with the eav(end of active video) reference code at the beginning of the digital line. bits p0, p1, p2, p3, have states dependent on the states of the bits f, v and h as shown below. at the receiver this permits one-bit errors to be corrected and two-bits errors to be detected. error correction a = p1 xor f xor v b = p2 xor f xor h c = p3 xor v xor h d = f xor v xor h xor p3 xor p2 xor p1 xor p0 f = f xor (d a b c# ) v = v xor (d a b# c) h = h xor (d a# b c) sav/eav one-bit error occurs when d (a + b + c) sav/eav two-bit error occurs when d# (a + b + c) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 21 digital video 16-bit input video 16 (cr0d[7:6] = 00) total input 17bits(2 byte parallel data and 1 pin for clock) the red part is the timing rtd generate internally. ff 00 00 sav y0 cb0 y1 cr1 ff 00 00 eav y719 cr718 ena/hsync vsync/odd video 16(cr0d[7:6] = 01) c video16(1) ? sav/eav ??? 00 ff sav 00 y0 cb0 y1 cr1 00 ff eav 00 y719 cr718 ena/hsync vsync/odd video 16(cr0d[7:6] = 10) itu1120 timing. 00 00 sav sav y0 cb0 y1 cr1 ff ff 00 00 y719 cr718 ena/hsync vsync/odd 00 ff ff 00 00eav eav 00 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 22 video 16 (cr0d[7:6] = 11) there are extra input control signal ena, hsync, vsync and odd signal. y0y1y2y3 y4 u0v0u2 v2 u4 clk y cbcr ena analog input rtd integrates three adc s (analog-to-digital converters), one for each color (red, green, and blue). the sync-processor can deal with separate-sync, composite-sync, and sync-on-green. and the pll can generate very low jitter clock from hs to sample the analog signal to digital data. input data is latched within a capture window defined in registers refer to vs and hs leading edge. rtd also has 2 adc input, we can switch these 2 input to choose which input we want to present on rtd embedded lcd monitor. rtd has a ypbpr input, we can connect dvd or some devices that has ypbpr input, ypbpr input can be 1 st or 2 nd adc pins. tmds input rtd integrates high-speed single link receiver function. it can operate up to 165 m at long cable. rtd integrates an equalizer to enhance the cable loss weakness in long cable application and the advanced tracking algorithm to have better performance in dvi rx. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 23 input capture window inside rtd, there are four registers iph_act_sta, iph_act_wid, ipv_act_sta & ipv_act_len to define input capture window for the selected input video on either a or b input port while programmed analog input mode. the horizontal sync (ihs) & vertical sync (ivs) signals are used from the selected port to determine the capture window region. ihs input capture window iph_act_sta iph_act_wid vertical blanking region (front porch) vertical blanking region (back porch) horizontal blanking region (front porch) horizontal blanking region (back porch) ipv_act_sta ipv_act_len ivs figure 3 input capture window http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 24 3.2 output timing display output timing the display output port sends single/double pixel data transfer and synchronized display timing to an external device. the display port also support display panel with 6-bit per color, turn on the dithering function to enhance color depth. in single pixel output mode, single pixel data (24-bit rgb) is transferred to display port a on each active edge of dclk, the rate of dclk is also equal to display pixel clock. the sync & enable signals are also sent to display port on each active edge of dclk. in double pixel output mode, double pixel data (48-bit rgb) is transferred to display port a & b on each active edge of dclk and the rate of dclk is equal to half display pixel clock at this moment. the sync & enable signals are also sent to display port on each active edge of dclk. dclk db/rgb den xxx da/rgb xxxrgb0rgb1rgb2rgb3rgb4rgb5 figure 4 ttl single pixel mode display data timing dhclk da/rgb den xxxrgb0rgb2rgb4rgb6rgb8rgb10 db/rgb xxxrgb1rgb3rgb5rgb7rgb9rgb11 figure 5 ttl double pixel mode display data timing http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 25 figure 6 lvds 18bit display timing figure 7 lvds 24 bit display timing http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 26 figure 8 rsds type3 display timing http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 27 display active window these registers define the display active window shown below in application of frame sync mode. refer to the register description for detail. dhs dh_bkgd_sta dh_act_sta vertical blanking region (front porch) vertical blanking region (back porch) horizontal blanking region (front porch) horizontal blanking region (back porch) dv_bkgd_sta dv_act_end den display active window background region dvs dh_hs_end dh_act_end dh_bkgd_end dh_total dv_vs_end dv_act_sta dv_bkgd_end dv_total figure 9 display active window diagram http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 28 3.3 color processing digital color r & g & b independent channel srgb, contrast, brightness, gamma, dithering controls are built in rtd. srgb compliance function is provided with 9 multipliers. the contrast control is performed a multiply value from 0 to 2 for each r/g/b channel. the brightness control is used to set an offset value from C 512 to +511 also for each r/g/b channel. also rtd provided 10 bit gamma and a high performance dithering function. 3.4 osd & color lut build-in osd the detailed function-description of build-in osd, please refer to the application note for rtd embedded osd. color lut & overlay port the following diagram presents the data flow among the gamma correction, dithering, overlay mux, osd lut and output format conversion blocks. gamma correction dithering output format convert mux u8 u8.2 internal osd background color u10 + u8.2 u8 figure 10 osd color look-up table data path diagram http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 29 3.5 auto-adjustment there are two main independent auto-adjustment functions supported by rtd, including auto-position & auto-tracking. the operation procedure is as following; auto-position 1. define the rgb color noise margin: when the value of color channel r or g or b is greater than these noise margins, a valid pixel is found. 2. define the threshold-pixel for vertical boundary search 3. define the boundary window of searching for horizontal boundary search. 4. start auto-function. 5. the result can be read from register. auto-tracking 1. setting the control-registers for the function (auto-phase, auto-balance) according to the control-table. 2. define the threshold 3. define the boundary window of searching for tracking window. 4. start auto-function. 5. the result can be read from register 3.6 pll system inside the rtd, there are four pll systems for display clock and adc sample clock (pll1, pll2, m2pll, dpll ). dclk pll dpll frequency = f_in * dpm / dpn * divider. f_in is input crystal frequency. dpm and dpn is in dpll_m and dpll_n . divider is in dpll_n , and it divide pll frequency by 1, 2, 4 or 8. according to parameter dpn, you must set lpf mode in dpll_wd . if lpf mode is 1, the charge pump current, ich, must be dpm/17.6, while ich must be dpm/1.67 if lpf mode is 0. the charge pump current ich is in dpll_crnt . spread-spectrum function is also build in dclk to reduce emi. you can control the ssp_i, ssp_w, and fmdiv to fine-tune the emi. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 30 m2pll figure 11 m2pll system block diagram m2pll is a pll used to power-on reset, fifo clock and internal crystal clock. after power-on reset, m2pll output 10 times frequency of crystal clock. according to crystal frequency, set m2pll to keep fifo clock frequency between 240mhz and 250mhz. adc pixel sampling pll the input pixel sampling pll of rtd compose of pll1 and pll2 and dds, the hybrid pll system inherently has a process-independent advantages comparing with pure analog pll, dds synthesizer is in charge of the phase-frequency control, pll1 provided a high frequency to get a larger bandwidth letting the system fast locking, pll2 finally synthesize the desired pixel sampling clock. the block diagram shown below describes our high-performance tracking system. figure 12 apll system block diagram phase shifter pll 1 div pfd 1 pump loop vco div n2 div m2 hsync fbck ctrl signal 16 phase fav up dn icp vctrl fout pll 2 dds xtal m2pll 1/8 power-on reset fifo clock 1/10 or 1/11 internal xtal http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 31 3.7 host interface parallel/serial port determination: after reset end, the status of pin 5 (tmds_tst) can be sensed to determine the interface mode: high for parallel port, low, low for serial port. host interface location determination: after the falling edge of reset signal, the status of pin 3 can be sensed to determine the host interface location: high for 112-115,118,119, and low for 52-57 reset pin3 or pin5 falling edge to detect figure 13 serial/parallel port and host interface location selection http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 32 double data rate serial/parallel interface: any transaction should start from asserted the scsb low and stop after the scsb goes high. 100n d0 [4:0] d0 [8:5] d1 [4:0] d1 [8:5] scsb sclk sdiox adrh r/w inc adrl adrl inc/rw d0[4:0] d0[8:5] d1[4:0] d1[8:5] scsb sclk adrh figure 14 parallel port read (upper)/write (below) with dual edge data latch sdio0 adrl [a0] adrh[a4] r/w d0[0] d0[4] d1[0] d1[4] sdio1 adrl [a1] adrh[a5] inc d0[1] d0[5] d1[1] d1[5] sdio2 adrl [a2] adrh[a6] x d0[2] d0[6] d1[2] d1[6] sdio3 adrl [a3] adrh[a7] x d0[3] d0[7] d1[3] d1[7] parallel port data alignment a 1 scsb sclk a 2 a 0 a 3 a 4 a 5 a 6 a 7 r w i n c d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 a 1 scsb sclk a 2 a 0 a 3 a 4 a 5 a 6 a 7 r w i n c d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 a0 a1 a2 a3 a4 a5 a6 a7 r/w inc d0 d1 d2 d3 d4 d5 d6 d7 serial port read (upper)/write (below) with dual edge data latch, and serial port data alignment http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 33 3.8 reset output we have the reset_out function, and also reserve the reset_in function. by the bounding of internal pins we can select two kinds of reset function. first of all is only reset-out, we can output the reset signal to mcu, and the mcu can reset the rtd by firmware. the second is rtd output reset and also reset itself. notice that the reset output is positive polarity, besides, the reset output is open-drain pin, please don t forget to attach a pull-up resistor (10k). the reset function for 3.3v operating voltage detection is determined by 33vrst_ref voltage, no matter 5v or 3.3v mcu is been used, divider the input voltage on 33vrst_ref to 2.2v for internal power sensing circuit detecting, the divider resistor should be 10k level avoiding current leakage. figure 15 three kinds of reset function for the reset-out function, the characteristics are below: parameter symbol min. typ. max. unit detection voltage -v det 1.8 2.4 v release voltage +v det - 2.6 - v delay time td 50 - - ms reset in resetb reset out package die http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 34 3.9 the programmable schmitt trigger of hsync to get better waveform of the input hsync, we have a programmable schmitt trigger circuit. for different hsync amplitude and polarity, we can select different setting of the threshold voltage. the v t + and the v t - can be selected by register cr97 we can select the old mode or the new mode. when using the new mode we can directly determine the positive threshold voltage (1.4v, 1.6v 2.6v), and we can choose the hysterias from the v t + to determine the v t - (0.6v, 0.8v, 1.0v, 1.2v). we also can finely tune the voltage by minus 0.1v. for application, we can select different threshold voltage by the polarity of the hsync. the control register is cr97 figure 16 the schmitt trigger behavior diagram 3.10 crystal frequency output rtd can output crystal frequency or 1/2 crystal frequency to external mcu to save a crystal device. once power state is on and reset is finished, we can set crystal frequency by firmware and output to pin 48 and pin 110 simultaneously, and then can turn off them in pin share part. pin 48 and pin 110 is configurable, detail setting is listed in pin-share part v t - v t + input hsync output hsync http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 35 4. register description global event flag reading unimplemented registers will return 0. address: 00 id_reg default: a1h bit mode function 7:0 r msb 4 bits: 1010 product code lsb 4 bits: 0001 rev. code address: 01 hostctrl default: 02h bit mode function 7 r display support 0: up to sxga 1: up to uxga 6:3 r/w reserved to 0 2 r/w power down mode enable 0: normal (default) 1: enable power down mode turn off adc r/g/b/banggap/dpll/lvds/pll1/pll2/sog/sync proc/tmds 1 r/w power saving mode enable 0: normal 1: enable power saving mode (default) turn off adc r/g/b/dpll/lvds/pll1/pll2 0 r/w software reset whole chip (low pulse at least 8ms) 0: normal (default) 1: reset (all registers are reset to default except host_ctrl & m2pll & cout frequency (tcon00[3]), the only difference with hardware-reset is power on latch won t work) address: 02 status0 (status0 register) default: 00h bit mode function 7 r adc_pll non-lock: if the adc_pll non-lock occurs, this bit is set to 1 . 6 r input vsync error if the input vertical sync occurs within the programmed active period, this bit is set to 1 . 5 r input hsync error if the input horizontal sync occurs within the programmed active period, this bit is set to 1 . 4 r input odd toggle occur (for internal field odd toggle, refer to cr0f[5]) if the odd signal (from sav/eav or v16_odd) toggle occurs, this bit is set to 1 . http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 36 3 r video8/16 input vertical/horizontal sync occurs if the yuv input v or h sync edge occurs, this bit is set to 1 . 2 r adc input vertical/horizontal sync occurs input v or h sync edge occurs; this bit is set to 1 . this mechanism refers to current selected adc,(i.e.: we can choose from adc0/adc1) 1 r input overflow status (frame sync mode) if an overflow in the input data capture buffer occurs, this bit is set to 1 . 1 0 r line buffer underflow status (frame sync mode) if an underflow in the line-buffer occurs, this bit is set to 1 . write to clear status. address: 03 status1 (status1 register) default: 00h bit mode function 7 r line buffer overflow status 2 1: line buffer overflow has occurred since the last status cleared 6 r line buffer underflow status 1: line buffer underflow has occurred since the last status cleared 5 r dena stop event status 1: if the dena stop event occurred since the last status cleared 4 r dena start event status 1: if the dena start event occurred since the last status cleared 3 r dvs start event status 1: if the dvs start event occurred since the last status cleared 2 r iena stop event status 1: if the iena stop event occurred since the last status cleared 1 r iena start event status 1: if the iena start event occurred since the last status cleared 0 r ivs start event status 1: if the ivs start event occurred since the last status cleared write to clear status. address: 04 irq_ctrl0 (irq control register 0) default: 00h bit mode function 7 r/w internal irq enable: (global) 0: disable these interrupt. 1 only the first event of input overflow/underflow will be recorded at the same time. 2 both input overflow/underflow status will be recorded whenever it happens. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 37 1: enable these interrupt. the irq event of crf9 & cr04 will be logically or together. 6 r/w irq (adc_pll non-lock) 0: disable the adc_pll non-lock error event as an interrupt source 1: enable the adc_pll non-lock error event as an interrupt source 5 r/w irq (input vsync/hsync error) (den across vsync or hsync) 0: disable the input vsync/hsync error event as an interrupt source 1: enable the input vsync/hsync error event as an interrupt source 4 r/w irq (input odd toggle occur) (eav/sav from video8/16 or v16_odd) 0: disable the input odd toggle event as an interrupt source 1: enable the input odd toggle event as an interrupt source 3 r/w irq (video8/16 input hsync/vertical sync occurs) 0: disable the video8/16 input hsync or vsync event as an interrupt source 1: enable the video8/16 input hsync or vsync event as an interrupt source 2 r/w irq (adc input hsync/vertical sync occurs) 0: disable the adc input hsync or vsync event as an interrupt source 1: enable the adc input hsync or vsync event as an interrupt source 1 r/w irq (line buffer underflow/overflow status) 0: disable the line buffer underflow/overflow event as an interrupt source 1: enable the line buffer underflow/overflow event as an interrupt source 0 -- reserved to 0 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 38 input video capture address: 05 vgip_ctrl (video graphic input control register) default: 00h bit mode function 7 r/w 8 bit random generator 0: disable(default) 1: enable 6 r/w input test mode: 0: disable (default) 1: video8 input will go through rgb channel, avs=>ivs, ahs=>ihs, vclk=>iclk 5 r/w vgip double buffer ready 0: not ready to apply 1: ready to apply l when the list table of cr05 [4] is set, then enable cr05 [5], finally, hardware will auto load these value into rtd as the trigger event happens and clear cr05 [5] to 0. 4 r/w vgip double buffer mode enable(each register describe below has its own double buffer) 0: disable (original- write instantly by mcu write cycles) 1: enable (double buffer function write mode) register trigger event iph_act_sta (cr09,cr0a) iden stop (falling edge of iden) ipv_act_sta (cr0d,cr0e) iv_dv_lines (cr40) iden stop (falling edge of iden) ihs delay (for capture) (cr12, cr13[0]) iden stop (falling edge of iden) pllphase(crab,crac) add 1-clk delay to ihs delay (cr07[4]) hsync synchronize edge (cr07[3]) iden stop (falling edge of iden) ivs_delay( for capture) (cr[11],cr13[1]) iden stop (falling edge of iden) 3:2 r/w input pixel format 00: embedded adc (adc_hs)(default) 01: embedded tmds 10: video 8 / 16 (cr0d[4] select from video8 and video16) 11: reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 39 1 r/w input graphic/video mode 0: from analog input (input captured by input capture window ) (default) 1: from digital input (captured start by enable signal , but sill stored in capture window size ) 0 r/w input sampling run enable 0: no data is transferred (default) 1: sampling input pixels address: 06 vgip_siginv (input control signal inverted register) default: 00h bit mode function 7 r/w safe mode 0: normal (default) 1: safe mode enable, mask 1 frame ivs of every 2 frame ivs, slow down input frame rate. 6 r/w ivs sync with ihs control (avoid vs bouncing) 0: enable (default) 1: disable 5 r/w hs signal inverted for field detection 0: negative edge (default) 1: positive edge 4 r/w input video odd signal invert enable 0: not inverted (odd = positive polarity) (default) 1: inverted (odd = negative polarity) 3 r/w input vs signal polarity inverted 0: not inverted (vs = positive polarity) (default) 1: inverted (vs = negative polarity) 2 r/w input hs signal polarity inverted 0: not inverted (hs = positive polarity) (default) 1: inverted (hs = negative polarity) 1 r/w input ena signal polarity inverted 0: not inverted (input high active) (default) 1: inverted (while input low active) 0 r/w input clock polarity 0: rising edge latched (default) 1: falling edge latched address: 07 vgip_delay_ctrl default: 00h bit mode function 7 r 6-iclk-delay hs level latched by vs rising edge http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 40 6 r hs level latched by vs rising edge 5 r hs level latched by 6-iclk-delay vs rising edge 4 r/w add one clock delay to ihs delay 0: disable (default) 1: enable 3 r/w hsync synchronize edge 0: hsync is synchronized by the positive edge of the input clock 1: hsync is synchronized by the negative edge of the input clock ( hsync source is selected by cr48[0] and then synchronized ) 2 r/w vsync synchronize edge 0: latch vs by the negative edge of input hsync(default) 1: latch vs by the positive edge of input hsync 1:0 r/w input clock delay control: 00: normal (default) 01: 1ns delay 10: 2ns delay 11: 3ns delay address: 08 vgip_odd_ctrl (video graphic input odd control register) default: 00h bit mode function 7 r/w odd invert for odd-controlled-ivs_delay. 0: not invert (default) 1: invert 6 r/w odd-controlled-ivs delay one line enable 0: disable (default) 1: enable l for both auto and capture 5 r/w safe mode odd inversion 0: not inverted (default) 1: inverted 4 r/w force odd toggle enable (without odd/even toggle select in safe mode) 0: disable (default) 1: enable 3 r/w video 4:2:2->4:4:4 enable before scale down (duplicate) 0: disable (default) 1: enable i.e. this bit should be always enable when in video8 / 16 mode. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 41 2 r/w decode video8 or video16 when adc or tmds active (cr0d[4] select from video8 and video16) 0: disable (default) 1: enable 1 r/w eav error correction enable in video8/16 0: disable 1: enable 0 r/w internal odd signal selection 0: odd signal from eav or ypbpr (default) 1: internal field detection odd signal (also support under vga, dvi input) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 42 input frame window (all capture window setting unit is 1) address: 09 iph_act_sta_h (input horizontal active start) default: 00h bit mode function 7 r/w input test output enable 0: disable (default) 1:test signals output to input_test_out [29:0] & input_clk output to adclk 6:4 r/w select color output to input_test_output [29:0] pin 102-97,94-85,82-73,70-67 000: 0, z0tst[3:0],adclk, red[7:0],green[7:0],blue[7:0] through vgip 001: 0, z0tst[3:0], adclk, red[7:0],green[7:0],blue[7:0] after scale down 010: 0, z0tst[3:0], adclk, ivs_dly, ihs_dly, ifd_odd, iena, vsd_den, vsd_act, auto_hs, auto_vs, auto_field, coast, hs_out, clamp, phase_error, sog_in, fav,msb2_signal, tmds_dbg_out[7:0] 011: 0, z0tst[3:0],adclk, 0, mcuwr, mcurd, mcu_adr_inc, min[7:0], madr[7:0], sdmout_tst[3:0], 100: 0, z0tst[3:0], adclk, raw_vs, raw_hs, raw_odd, raw_den, sdmout_tst[3:0], 0,0,0,0, green[7:0], red[7:0] through vgip 101: 0, z0tst[3:0], adc_clk, adc_clk, raw_vs, raw_hs, en _flag, red[7:0], green[7:0], meas_ihs, hsout, coast, 1'b0 110: 0, z0tst[3:0], adc_clk, adc_clk, raw_vs, raw_hs, raw_filed, blue[7:0], green[7:0], hs0_schmitt, hs1_schmitt, 2'd0 111: 0, z0tst[3:0], adc_clk , iclk_tst, raw_vs, raw_hs, raw_filed, tmds_dbg_ou t[7:0], green[7:0], fifo_clk, internal_crystal, 2'd0 3 -- reserved 2:0 r/w input video horizontal active start -- high byte [10:8] address: 0a iph_act_sta_l (input horizontal active start low) default: 00h bit mode function 7:0 r/w input video horizontal active start -- low byte [7:0] l in analog mode, the number of pixel clocks from the leading edge of hs to the first pixel of the active line. target = iph_act_sta(>=2) +2, l in digital mode, the iph_act_sta is actually the same as it set. address: 0b iph_act_wid_h (input horizontal active width high) default: 00h bit mode function 7 r/w video8 / video16_c port input latch bus msb to lsb swap control: 0: normal (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 43 1: switched video8 / video16_c port msb to lsb sequence into lsb to msb 6 r/w adc input g/b swap 0: no swap 1: swap 5 r/w adc input r/b swap 0: no swap 1: swap 4 r/w adc input r/g swap 0: no swap 1: swap 3 r/w double clock input 0: single clock 1: double clock this bit should be set double clock when using video 8 input 2:0 r/w input video horizontal active width C high byte [10:8] b g rr g b cr0b[4]cr0b[5]cr0b[6] rtd address: 0c iph_act_wid_l (input horizontal active width low) default: 00h bit mode function 7:0 r/w input video horizontal active width -- low byte [7:0] this register defines the number of active pixel clocks to be captured. address: 0d ipv_act_sta_h (input vertical active start high) default: 00h bit mode function 7:6 r/w video16 mode (reference to digital video 16-bit input) 5 r/w video16_y / video16_c swap 0: disable 1: enable 4 r/w video8 / video16 select 0: video8 1: video16 3 r/w video16_y port input latch bus msb to lsb control: 0: normal (default) 1: switched video16_y port msb to lsb sequence into lsb to msb http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 44 2:0 r/w input video vertical active start C high byte [10:8] address: 0e ipv_act_sta_l (input vertical active start low) default: 00h bit mode function 7:0 r/w input video vertical active start C low byte [7:0] the numbers of lines from the leading edge of selected input video vsync to the first line of the active window. the value above should be larger than 1. address: 0f ipv_act_len_h (input vertical active lines) default: 00h bit mode function 7 r sav/eav two-bit error (write to clear) 6 r sav/eav one-bit error (write to clear) 5 r internal field detection odd toggle happen the function should be worked under no input clock 4:3 r the number of input hs between 2 input vs . lsb bit [1:0] 2:0 r/w input video vertical active lines C high byte [10:8] address: 10 ipv_act_len_l (input vertical active lines) default: 00h bit mode function 7:0 r/w input video vertical active lines C low byte [7:0] this register defines the number of active lines to be captured. address: 11 ivs_delay (internal input-vs delay control register) default: 00h bit mode function 7:0 r/w input vs delay count by input hsync [7:0] it s ivs delay for capture and digital filter, not for auto function address: 1 2 ihs_delay (internal input-hs delay control register) default: 00h bit mode function 7:0 r/w input hs delay count by input clock [7:0] it s ihs delay for capture and digital filter, not for auto function address: 13 vgip_hv_delay default: 00h bit mode function 7:6 r/w input hs delay count by input clock for auto function 00: no delay 01: 32 pixels 10: 64 pixels 11: 96 pixels 5:4 r/w input vs delay count by input hsync for auto function 00: no delay http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 45 01: 3 line 10: 7 line 11: 15 line 3:2 -- reserved to 0 1 r/w input vs delay count by input hsync[8] 0 r/w input hs delay count by input clock[8] fifo window address: 14 drl_h_bsu (display read high byte before scaling-up) default: 00h bit mode function 7 -- reserved 6:4 r/w display window read width before scaling up: high byte [10:8] 3 -- reserved 2:0 r/w display window read length before scaling up: high byte [10:8] address: 15 drw_l_bsu (display read width low byte before scaling-up) default: 00h bit mode function 7:0 r/w display window read width before scaling up: low byte [7:0] address: 16 drl_l_bsu (display read length low byte before scaling-up) default: 00h bit mode function 7:0 r/w display window read length before scaling up: low byte [7:0] l the setting above should be use 2 as unit ihs_delay cr13[0] / cr12 ihs_delay for auto cr13[7:6] 1 clk delay cr07[4] for capture for auto ihs ivs_delay cr13[1] / cr11 ivs_delay for auto cr13[5:4] for capture for auto ivs figure 17 ihs_delay path diagram digital filter address: 17 digital_filter_ctrl default: 00h bit mode function 7:4 r/w access port write enable 0000: disable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 46 0001: phase access port 0010: negative smear access port 0011: positive smear access port 0100: negative ringing access port 0101: positive ringing access port 0110: mismatch access port 0111: y(b)/pb(g)/pr(r) channel digital filter enable 1xxx: noise reduction access port 3:2 r/w two condition occur continuous (ringing to smear) 00: disable( hardware is off , depend on firmware) 01: only reduce ringing condition 10: only reduce smear condition 11: no adjust (hardware is on, but do nothing) 1 r/w when noise reduction and mismatch occur, select 0: mismatch 1: noise reduction 0 -- reserved to 0 address: 18 digital_filter_port digital_filter_ctrl [7:4] = 0111 default: 00h bit mode function 7 r/w y en (g) : function enable 0: function disable 1: function enable 6 r/w pb en (b) : function enable 0: function disable 1: function enable 5 r/w pr en (r) : function enable 0: function disable 1: function enable 4 r/w initial value : 0: raw data 1: extension 3:0 -- reserved to 0 bit7~5 only support both y_en(100) and rgb enable (111). digital_filter_port digital_filter_ctrl[7:5] = 000 ~ 110 default: 00h bit mode function 7 r/w en : function enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 47 0: function disable 1: function enable 6:4 r/w thd_offset threshold value of phase and mismatch and noise reduction or offset value of smear and ringing 3:2 r/w div: divider value of phase and mismatch or offset value of smear and ringing 00: 0 01: 1 10: 2 11: 3 1:0 -- reserved to 0 thd_offset define: the thd value definition of phase enhance function bit6~4 000 001 010 011 100 101 110 111 value 112 128 144 160 176 192 208 224 the offset value definition of smear and ringing reduce function bit6~4 000 001 010 011 100 101 110 111 value no use 16 32 48 64 80 96 112 the thd value definition of mismatch enhance function bit6~4 000 xx1 value 1 2 the thd value definition of noise reduction function bit6~4 000 001 010 011 100 101 110 111 value 0 1 2 3 4 5 6 7 scaling up function address: 19 scale_ctrl (scale control register) default: 00h bit mode function 7 r/w video mode compensation: 0: disable (default) 1: enable 6 r/w internal odd-signal inverse for video-compensation 0: no invert (default) 1: invert 5 r display line buffer ready http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 48 0: busy 1: ready 4 r/w enable full line buffer: 0: disable (default) 1: enable 3 r/w vertical line duplication 0: disable 1: enable 2 r/w horizontal pixel duplication 0: disable 1: enable 1 r/w enable the vertical filter function: 0: by pass the vertical filter function block (default) 1: enable the vertical filter function block 0 r/w enable the horizontal filter function: 0: by pass the horizontal filter function block (default) 1: enable the horizontal filter function block l when using h/v duplication mode, fifo window width set original width, but fifo width height should be 2x the original height. address: 1a sf_access_port default: 00h bit mode function 7 r/w enable scaling-factor access port 6:5 -- reserved to 0 4:0 r/w scaling factor port address l when disable scaling factor access port, the access port pointer will reset to 0 address: 1b-00 hor_sca_h (horizontal scale factor high) bit mode function 7:4 -- reserved 3:0 r/w bit [19:16] of horizontal scale factor address: 1b-01 hor_sca_m (horizontal scale factor medium) bit mode function 7:0 r/w bit [15:8] of horizontal scale factor address: 1b-02 hor_sca_l (horizontal scale factor low) bit mode function 7:0 r/w bit [7:0] of horizontal scale factor address: 1b-03 ver_sca_h (vertical scale factor high) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 49 bit mode function 7:4 -- reserved 3:0 r/w bit [19:16] of vertical scale factor address: 1b-04 ver_sca_m (vertical scale factor medium) bit mode function 7:0 r/w bit [15:8] of vertical scale factor address: 1b-05 ver_sca_l (vertical scale factor low) bit mode function 7:0 r/w bit [7:0] of vertical scale factor this scale-up factor includes a 20-bit fraction part to present a vertical scaled up size over the stream input. for example, for 600-line original picture scaled up to 768-line, the factor should be as follows: (600/768) x 2^20 = 0.78125 x 2^20 = 819200 = c8000h = 0ch, 80h, 00h. address: 1b-06 horizontal scale factor segment 1 pixel default: 00h bit mode function 7:3 -- reserved 2:0 r/w bit [10:8] of scaling factor segment 1 pixel address: 1b-07 horizontal scale factor segment 1 pixel default: 00h bit mode function 7:0 r/w bit [7:0] of scaling factor segment 1 pixel address: 1b-08 horizontal scale factor segment 2 pixel default: 00h bit mode function 7:3 -- reserved 2:0 r/w bit [10:8] of scaling factor segment 2 pixel address: 1b-09 horizontal scale factor segment 2 pixel default: 00h bit mode function 7:0 r/w bit [7:0] of scaling factor segment 2 pixel address: 1b-0a horizontal scale factor segment 3 pixel default: 00h bit mode function 7:3 -- reserved 2:0 r/w bit [10:8] of scaling factor segment 3 pixel address: 1b-0b horizontal scale factor segment 3 pixel default: 00h bit mode function 7:0 r/w bit [7:0] of scaling factor segment 3 pixel address: 1b-0c horizontal scale factor delta 1 default: 00h bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 50 7:5 -- reserved 4:0 r/w bit [12:8] of horizontal scale factor delta 1 address: 1b-0d horizontal scale factor delta 1 default: 00h bit mode function 7:0 r/w bit [7:0] of horizontal scale factor delta 1 address: 1b-0e horizontal scale factor delta 2 default: 00h bit mode function 7:5 -- reserved 4:0 r/w bit [12:8] of horizontal scale factor delta 2 address: 1b-0f horizontal scale factor delta 2 default: 00h bit mode function 7:0 r/w bit [7:0] of horizontal scale factor delta 2 address: 1b-10 horizontal filter coefficient initial value default: c4h bit mode function 7:0 r/w accumulate horizontal filter coefficient initial value address: 1b-11 vertical filter coefficient initial value default: c4h bit mode function 7:0 r/w accumulate vertical filter coefficient initial value address: 1c filter_ctrl (filter control register) default: 00h bit mode function 7 r/w enable filter coefficient access 0: disable (default) 1: enable 6 r/w select h/v user defined filter coefficient table for access channel 0: 1 st coefficient table (default) 1: 2 nd coefficient table 5 r/w select horizontal user defined filter coefficient table 0: 1 st horizontal coefficient table (default) 1: 2 nd horizontal coefficient table 4 r/w select vertical user defined filter coefficient table 0: 1st vertical coefficient table (default) 1: 2 nd vertical coefficient table 3:0 -- reserved to 0 l the user defined filter coefficient table can be modified on-line. only the non-active coefficient-table can be modified, and then switch it to active. address: 1d filter_port (user defined filter access port) default: 00h http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 51 bit mode function 7:0 w access port for user defined filter coefficient table l when enable filter coefficient accessing, the first write byte is stored into the lsb(bit[7:0]) of coefficient #1 and the second byte is into msb (bit[8:11]). therefore, the valid write sequence for this table is c0-lsb, c0-msb, c1-lsb, c1-msb, c2-lsb, c2-msb c63-lsb & c63-msb, totally 64 * 2 cycles. since the 128 taps is symmetric, we need to fill the 64-coefficient sequence into table only. address: 1e osd_reference__den default: 00h bit mode function 7:0 r/w position of reference den for osd[7:0] address: 1f new_dv_ctrl default: 00h bit mode function 7 r/w new timing enable 0: disable 1: enable 6 r/w line compensation enable 0: disable 1: enable 5 r/w pixel compensation enable 0: disable 1: enable 4 r/w reserved to 0 3:0 r/w dclk_delay[11:8] address: 20 new_dv_dly default: 00h bit mode function 7:0 r/w dclk_delay[7:0] when cr 1f[7]=1, dclk_delay can t be 0 address: 21 reserved fifo frequency address: 22 fifo frequency default: 00h bit mode function 7 r/w test mode 0: disable 1: input data of vgip replaced by background color in cr6d http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 52 6:4 r/w reserved to 0 3 r/w m2pll_div 0: x 1/10 1: x 1/11 2 r/w internal xtal frequency 0: f xtal 1: f xtal * m2pll_m / m2pll_n * m2pll_div 1:0 r/w fifo frequency 00: m2pll 01: iclk 10: dclk 11: reserved scaling down control address: 23 scale_down_ctrl (scale down control register) default: 00h bit mode function 7 r bist for fifo ok 0: fail 1: ok 6 r bist for line buffer one & two ok 0: fail 1: ok 5 r/w fifo bist function start (auto clear to 0 when finish) 0: finish 1: start 4 r/w line buffer bist function start (auto clear to 0 when finish) 0: finish 1: start 3 r/w horizontal non-linear scale down 0: linear 1: non-linear 2 r/w vertical scale-down compensation 0: disable (default) 1: enable 1 r/w horizontal scale down function enable: http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 53 0: disable scale down function (default) 1: enable scale down function 0 r/w vertical scale down function enable: 0: disable scale down function (default) 1: enable scale down function address: 24 scale_down_access_port control default: 00h bit mode function 7 r/w enable scale-down access port 6:5 -- reserved to 0 4:0 r/w scale-down port address address: 25-00 v_scale_init bit mode function 7:6 -- reserved 5:0 r/w vertical scale down initial select [5:0] l scale down initial point select: for example, if the value is 43, we select the initial point is 43/64 address: 25-01 v_scale_dh (vertical scale down factor register) bit mode function 7:3 r/w reserved 2:0 r/w vertical scale down factor [18:16] address: 25-02 v_scale_dm (vertical scale down factor register) bit mode function 7:0 r/w vertical scale down factor [15:8] address: 25-03 v_scale_dl (vertical scale down factor register) bit mode function 7:0 r/w vertical scale down factor [7:0] l registers {v_scale_dh, v_scale_dm, v_scale_dl} = (yi/ym)*(2^17). l the largest scale down ratio is 1/4 (integer part 2 bits) l meanwhile, yi = vertical input length; ym=vertical memory write length address: 25-04 h_scale_init bit mode function 7:6 -- reserved 5:0 r/w horizontal scale down initial select [5:0] l scale down initial point select: for example, if the value is 43, we select the initial point is 43/64 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 54 address 25-05 h_scale_dh bit mode function 7:0 r/w horizontal scale down factor [23:16] address: 25-06 h_scale_dm bit mode function 7:0 r/w horizontal scale down factor [15:8] address: 25-07 h_scale_dl bit mode function 7:0 r/w horizontal scale down factor [7:0] l for linear scale down, registers {h_scale_dh, hscale_dm, hscale_dl} = (xi/xm)*(2^20). l meanwhile, xi = vertical input length; xm=vertical memory write length address: 25-08 h_scale_acch bit mode function 7 -- reserved 6:0 r/w horizontal scale down accumulated factor [14:8] address: 25-09 h_scale_accl bit mode function 7:0 r/w horizontal scale down accumulated factor [7:0] address: 25-0a sd_acc_widthh bit mode function 7:2 -- reserved 1:0 r/w horizontal scale down accumulated width [9:8] address: 25-0b sd_acc_widthl bit mode function 7:0 r/w horizontal scale down accumulated width [7:0] address: 25-0c sd_flat_widthh bit mode function 7:3 -- reserved 2:0 r/w horizontal scale down flat width [10:8] address: 25-0d sd_acc_widthl bit mode function 7:0 r/w horizontal scale down flat width [7:0] http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 55 peaking filter and coring control address: 26 peaking/coring access port control default: 00h bit mode function 7 r/w enable peaking / coring access port 6 r/w peaking/coring enable 0: disable 1: enable 5:3 -- reserved 2:0 r/w peaking/coring port address address: 27-00 peaking_coef0 bit mode function 7:0 r/w coefficient c0 of peaking filter: valid range: -128/32(-128) ~ 127/32 (127) (2 s complement) address: 27-01 peaking_coef1 bit mode function 7:0 r/w coefficient c1 of peaking filter: valid range: -128/32(-128) ~ 127/32 (127) (2 s complement) address: 27-02 peaking_coef2 bit mode function 7:0 r/w coefficient c2 of peaking filter: valid range: -128/32(-128) ~ 127/32 (127) (2 s complement) address: 27-03 coring_min bit mode function 7:5 r/w reserved 4:0 r/w coring minimum value address: 27-04 coring_max_pos bit mode function 7:0 r/w coring maximum positive value address: 27-05 coring_max_neg bit mode function 7:0 r/w coring maximum negitive value (2 s complement) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 56 display format address: 28 vdis_ctrl (video display control register) default: 20h bit mode function 7 r/w force display timing generator enable: (should be set when in free-run mode) 0: wait for input ivs trigger 1: force enable 6 r/w display data output inverse enable 0: disable (default) 1: enable (only when data bus clamp to 0) 5 r/w display output force to background color 0: display output operates normally 1: display output is forced to the color as selected by background color (cr6d) (default) 4 r/w display 18 bit rgb mode enable 0: all individual output pixels are full 24-bit rgb (default) 1: all individual output pixels are truncated to 18-bit rgb (lsb 2 bits = 0) 3 r/w frame sync mode enable 0: free running mode (default) 1: frame sync mode 2 r/w display output double port enable 0: single port output (default) 1: double port output in single-port mode for 6/8 bit ttl or rsds, you can select which port you want output, default is b port, and a port is set as tcon pin. when even/odd swap (cr29[6]) is set, a port is display output, b port is tcon pin. pin 101~106 output 0 for non-even/odd-swap single-port ttl/rsds. pin 77~82 output 0 for even/odd-swap single-port ttl/rsds. 1 r/w display output run enable 0: dhs, dvs, den & data bus are clamped to 0 (default) 1: display output normal operation. 0 r/w display timing run enable 0: display timing generator is halted, zoom filter halted (default) 1: display timing generator and zoom filter enabled to run normally steps to disable output: first set cr28[1]=0, set cr28[6], then set cr28[0]=0 to disable output. address: 29 vdisp_siginv (display control signal inverted) default: 00h bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 57 7 r/w dhs output format select (only available in frame sync ) 0: the first dhs after dvs is active (default) 1: the first dhs after dvs is inactive 6 r/w display data port even/odd data swap: 0: disable (default) 1: enable 5 r/w display data port red/blue data swap 0: disable (default) 1: enable 4 r/w display data port msb/lsb data swap 0: disable (default) 1: enable 3 r/w skew display data output 0: non-skew data output (default) 1: skew data output 2 r/w display vertical sync (dvs) output invert enable: 0: display vertical sync output normal active high logic (default) 1: display vertical sync output inverted logic 1 r/w display horizontal sync (dhs) output invert enable: 0: display horizontal sync output normal active high logic (default) 1: display horizontal sync output inverted logic 0 r/w display data enable (den) output invert enable: 0: display data enable output normal active high logic (default) 1: display data enable output inverted logic address: 2a dh_total_h (display horizontal total pixels) bit mode function 7:4 -- reserved to 0 3:0 r/w display horizontal total pixel clocks : high byte[11:8] address: 2b dh_total_l (display horizontal total pixels) bit mode function 7:0 r/w display horizontal total pixel clocks: low byte[7:0] real dh_total (target value)= dh_total (register value)+ 4 address: 2c dh_hs_end (display horizontal sync end) bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 58 7:0 r/w display horizontal sync end[7:0]: determines the width of dhs pulse in dclk cycles address: 2d dh_bkgd_sta_h (display horizontal background start) bit mode function 7:4 -- reserved 3:0 r/w display horizontal background start : high byte [11:8] address: 2e dh_bkgd_sta_l (display horizontal background start) bit mode function 7:0 r/w display horizontal background start : low byte [7:0] determines the number of dclk cycles from leading edge of dhs to first pixel of background region. real dh_bkgd_sta (target value)= dh_bkgd_sta (register value)+ 10 address: 2f dh_act_sta_h (display horizontal active start) bit mode function 7:4 -- reserved 3:0 r/w display horizontal active region start : high byte [11:8] address: 30 dh_act_sta_l (display horizontal active start) bit mode function 7:0 r/w display horizontal active region start : low byte [7:0] determines the number of dclk cycles from leading edge of dhs to first pixel of active region. real dh_act_sta (target value)= dh_act_sta (register value)+ 10 address: 31 dh_act_end_h (display horizontal active end) bit mode function 7:4 -- reserved 3:0 r/w display horizontal active end : high byte [11:8] address: 32 dh_act_end_l (display horizontal active end) bit mode function 7:0 r/w display horizontal active end : low byte [7:0] determines the number of dclk cycles from leading edge of dhs to the pixel of background region. real dh_act_end (target value)= dh_act_end (register value)+ 10 address: 33 dh_bkgd_end_h (display horizontal background end) bit mode function 7:4 -- reserved 3:0 r/w display horizontal background end : high byte [11:8] address: 34 dh_bkgd_end_l (display horizontal background end) bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 59 7:0 r/w display horizontal background end : low byte [7:0] real dh_bkgd_end (target value) = dh_bkgd_end (register value)+ 10 address: 35 dv_total_h (display vertical total lines) bit mode function 7:4 -- reserved to 0 3:0 r/w display vertical total : high byte [11:8] address: 36 dv_total_l (display vertical total lines) bit mode function 7:0 r/w display vertical total: low byte [7:0] cr35, cr36 use as watch dog reference value in frame sync mode, the event should be the line number of display hs is equal to dv total. address: 37 dvs_end (display vertical sync end) bit mode function 7:5 -- reserved 4:0 r/w display vertical sync end[4:0]: determines the duration of dvs pulse in lines address: 38 dv_bkgd_sta_h (display vertical background start) bit mode function 7:4 -- reserved 3:0 r/w display vertical background start: high byte [11:8] determines the number of lines from leading edge of dvs to first line of background region. address: 39 dv_bkgd_sta_l (display vertical background start) bit mode function 7:0 r/w display vertical background start: low byte [7:0] address: 3a dv_act_sta_h (display vertical active start) bit mode function 7:4 -- reserved 3:0 r/w display vertical active region start: high byte [11:8] determines the number of lines from leading edge of dvs to first line of active region. address: 3b dv_act_sta_l (display vertical active start) bit mode function 7:0 r/w display vertical active region start: low byte [7:0] address: 3c dv_act_end_h (display vertical active end) bit mode function 7:4 -- reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 60 3:0 r/w display vertical active region end: high byte [11:8] address: 3d dv_act_end_l (display vertical active end) bit mode function 7:0 r/w display vertical active region end : low byte [7:0] determine the number of lines from leading edge of dvs to the line of following background region. address: 3e dv_bkgd_end_h (display vertical background end) bit mode function 7:4 -- reserved to 0 3:0 r/w display vertical background end: high byte [11:8] address: 3f dv_bkgd_end_l (display vertical background end) bit mode function 7:0 r/w display vertical background end: low byte [7:0] determine the number of lines from leading edge of dvs to the line of start of vertical blanking. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 61 frame sync fine tune address: 40 ivs2dvs_dealy_lines (ivs to dvs lines) default: 00h bit mode function 7:0 r/w ivs to dvs lines: (only for framesync mode) the number of input hs from ivs to dvs. should be double buffer by cr05[5:4] address: 41 iv_dv_delay_clk_odd (frame sync delay fine tuning) default: 00h bit mode function 7:0 r/w frame sync mode delay fine tune [7:0] 00 to disable applied to all fields when interlaced_fs_delay_fine_tuning is disabled (cr43[1] = 0) only for odd-field when interlaced_fs_delay_fine_tuning is enabled (cr43[1] = 1) in frame sync mode , cr40[7:0] represents output vs delay fine-tuning. for example, it delays the number of (cr41 [7:0] *16 + 16) input clocks. fill 00h, means 0, fill 01h, and means 32 address: 42 iv_dv_delay_clk_even (frame sync delay fine tuning) default: 00h bit mode function 7:0 r/w frame sync mode delay fine tune [7:0] 00 to disable only for even-field when interlaced_fs_delay_fine_tuning is enabled (cr43[1] = 1) address: 43 fs_delay_fine_tuning default: 00h bit mode function 7:2 r/w reserved to 0 1 r/w interlaced_fs_delay_fine_tuning 0: disable (default) 1: enable 0 r/w internal odd-signal inverse for interlaced_fs_delay_fine_tuning 0: no invert (default) 1: invert address: 44 last_line_h default: 00h bit mode function 7 r/w last-line-width / dv-total selector : 0: cr44 [3:0] and cr45 indicate last-line width counted by display clock (default) 1: cr44 [3:0] and cr45 indicate dhs total number between 2 dvs. 6 r/w dv sync with 4x clock 0: disable 1: enable 5 r/w bist test enable 0: disable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 62 1: enable (auto clear when finish) 4 r/w bist test result 0: fail 1: ok 3:0 r dv total or last line width[11:8] before sync in frame sync mode address: 45 last_line_l bit mode function 7:0 r dv total or last line width[7:0] before sync in frame sync mode display fine tune address: 46 dis_timing (display clock fine tuning register) default: 00h bit mode function 7 r/w reserved to 0 6:4 r/w display output clock fine tuning control: 000: dclk rising edge correspondents with output display data 001: 1ns delay 010: 2ns delay 011: 3ns delay 100: 4ns delay 101: 5ns delay 110: 6ns delay 111: 7ns delay 3 r/w aclk/bclk output enable ( only used in 6 bit ttl/smart panel, otherwise, use dclk) 0: disable 1: enable 2 r/w aclk(6 bit)/dclk(8 bit) polarity inverted 0: disable 1: enable 1 r/w dclk output enable (only been used in ttl 8 bit mode) 0: disable 1: enable 0 r/w bclk(6 bit) polarity inverted 0: non-inverted 1: inverted http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 63 sync processor address: 47 sync_select default: 00h bit mode function 7 r/w sync processor power down (stop crystal clock in) 0: normal run (default) 1: power down 6 r/w hysnc type detection auto run 0: manual (default) 1: automatic 5 r/w de-composite circuit enable 0: disable (default) 1: enable 4 r/w input hs selection 0 : hs_raw(ss/cs) (default) 1: sog/soy 3 r/w sog source selection 0: sog0/soy0 (default) 1: sog1/soy1 2 r/w adc hs/vs source 0: 1 st hs/vs (default) 1: 2 nd hs/vs 1 r/w measured by crystal clock (result showed in cr59) (in digital mode) 0: input active region (vertical iden start to iden stop) (measure at iden stop) (default) 1: display active region(vertical den start to den stop) (measure at den stop) the function should work correctly when ivs or dvs occurs and enable by cr50[4]. 0 r/w hsync & vsync measured mode 0: hs period counted by crystal clock & vs period counted by hs (analog mode) (default) 1: h resolution counted by input clock & v resolution counted by ena (digital mode) (get the correct resolution which is triggered by enable signal, ena) address: 48 sync_invert default: 00h bit mode function 7 r/w coast signal invert enable: 0: not inverted (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 64 1: inverted 6 r/w coast signal output enable: 0: disable (default) 1: enable 5 r/w hs_out signal invert enable: 0: not inverted (default) 1: inverted 4 r/w hs_out signal output enable: 0: disable (default) 1: enable 3 r/w cs_raw inverted enable 0: normal (default) 1: invert 2 r/w clamp signal output enable 0: disable (default) 1: enable 1 r/w hs recovery in coast 0: disable (default) (ss/soy) 1: enable (cs or sog ) 0 r/w hsync synchronize source 0: ahs (default) 1: feedback hs address: 49 sync_ctrl (sync control register) default: 02 h bit mode function 7 r/w clk inversion to latch feedback hs for coast recovery ( coast recovery means hs feedback to replace input hs) 0: non inversion (default) 1: inversion 6 r/w select hs_out source signal 0: bypass (sehs)(use in separate mode) 1: select de-composite hs out(dehs) (in composite mode) 5 r/w select adc_vs source signal (auto switch in auto run mode) 0: vs_raw 1: devs 4 r/w clk inversion to latch adc hs for clamp 0: non inversion (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 65 1: inversion 3 r/w inversion of hs to measure vsync 0: non inversion (default) 1: inversion 2 r/w hsync measure source(adc_hs) 0: select adc_hs (default) 1: select sehs or dehs by cr49[6] 1:0 r/w measure hsync/vsync source select: 00: tmds 01: video8/video16 10: adc_hs1/adc_vs (default) 11: cs_raw/vs_raw address: 4a stable_high_period_h bit mode function 7 r even/odd field of ypbpr 0: even 1: odd 6 r the toggling of polarity of ypbpr field happens 0: no toggle 1: toggle 5:3 r the number of input hs between 2 input vsync . lsb bit [2:0] for ypbpr 2:0 r stable high period[10:8] compare each line s high pulse period, if we get continuous 64 lines with the same one, the period is updated as the stable period. address: 4b stable_high_period_l bit mode function 7:0 r stable high period[7:0] compare each line s high pulse period, if we get continuous 64 lines with the same one, the period is updated as the stable period. address: 4c vsync_counter_level_msb default: 03h bit mode function 7 r hysnc type detection auto run result ready 6:4 r hysnc type detection auto run result 000: no signal 001: not support http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 66 010: ypbpr 011: serration composite sync 100: xor/or-type composite sync with equalizer 101: xor/or-type composite sync without equalizer 110: hsync with vs_raw (separate hsync) 111: hsync without vs_raw (hsync only) reference when hsync type detection auto run result ready (cr4c[7]) 3 r/w 2 nd adc/video switch 0: 2 nd adc (default) 1: video8 2:0 r/w vsync counter level count [10:8] msb vsync detection counter start value. address: 4d vsync_counter_level_lsb default: 00h bit mode function 7:0 r/w vsync counter level count [7:0] lsb address: 4e hsync_type_detection_flag bit mode function 7 r hs overflow(16-bits) 6 r stable period change (write clear when cr4e[6]=1 or cr4f[0]=1) 5 r stable polarity change (write clear when cr4e[5]=1 or cr4f[0]=1) 4 r vs_raw edge occurs (only use in auto run mode) if vs_raw edge occurs, this bit is set to 1 . 3 r detect capture window unlock repeated 32 times (write clear when cr4e[3]=1 or cr4f[0]=1) 2 r hsync have equalization (write clear when cr4e[2]=1 or cr4f[0]=1) 1 r hsync polarity change (write clear when cr4e[1]=1 or cr4f[0]=1) 0 r detect capture window unlock (write clear when cr4e[0]=1 or cr4f[0]=1) address: 4f stable_measure default: 00h bit mode function 7 r stable flag 0: period or polarity can t get continuous stable status. 1: both polarity and period are stable. 6 r stable polarity 0: negative http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 67 1: positive compare each line s polarity; if we get continuous n 64 lines with the same one, the polarity is updated as the stable polarity. 5:4 r/w feedback hsync high period select by adc clock: 00: 32 (default) 01: 64 10: 96 11: 128 3 r/w stable period tolerance 0: 2 crystal clks (default) 1: 4 crystal clks 2 r/w vsync measure invert enable 0: disable (default) 1: enable 1 r/w pop up stable value 0: no pop up (default) 1: pop up result, (cr4a[2:0], cr4b[7:0], cr4e[3], cr50[2:0], cr51[7:0]) 0 r/w stable measure start 0 : stop (default) 1 : start address: 50 stable_period_h default: 00h bit mode function 7 -- reserved 6 r cs_raw inverted by auto run mode 0: not inverted 1: inverted 5 r/w hs_out bypass pll into vgip 0: disable (default) 1: enable 4 r/w active region measure enable 0: disable (default) 1: enable 3 r/w adc_vs source select in test mode 0: select adc_vs source in normal mode or auto mode by cr47[6] (default) 1: select adc_vs source in test mode (select vs_raw or devs by cr49[5]) 2:0 r stable period[10:8] http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 68 compare each line s period, if we get continuous 64 lines with the same one, the period is updated as the stable period. address: 51 stable_period_l bit mode function 7:0 r stable period[7:0] compare each line s period, if we get continuous 64 lines with the same one, the period is updated as the stable period. address: 52 meas_hs_per_h (hsync period measured result) default: 8 b000xxxxx bit mode function 7 r/w on line auto measure enable 0: disable (default) 1: enable 6 r/w pop up period measurement result 0: no pop up (default) 1: pop up result 5 r/w start a hs & vs period / h & v resolution & polarity measurement (on line monitor) 0: finished/disable (default) 1: enable to start a measurement, auto cleared after finished 4 r over-flow bit of input hsync period measurement 0: no over-flow occurred 1: over-flow occurred 3:0 r input hsync period measurement result: high byte[11:8] address: 53 meas_hs_per_l (hsync period measured result) bit mode function 7:0 r input hsync period measurement result: low byte[7:0] l this result is expressed in terms of crystal clocks. l when measured digitally, the result is expressed as the number of input clocks between 2 input hs signals address: 54 meas_vs_per_h (vsync period measured result) bit mode function 7 r input vsync polarity indicator 0: negative polarity (high period is longer than low one) 1: positive polarity (low period is longer than high one) 6 r input hsync polarity indicator 0: negative polarity (high period is longer than low one) 1: positive polarity (low period is longer than high one) 5 r time-out bit of input vsync period measurement (no vsync occurred) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 69 0: no time out 1: time out occurred 4 r over-flow bit of input vsync period measurement 0: no over-flow occurred 1: over-flow occurred 3:0 r input vsync period measurement result: high byte[11:8] address: 55 meas_vs_per_l (vsync period measured result) bit mode function 7:0 r input vsync period measurement result: low byte[7:0] l this result is expressed in terms of input hs pulses. l when measured digitally, the result is expressed as the number of input ena signal within a frame. address: 56 meas_hs&vs_hi_h (hsync&vsync high period measured result) bit mode function 7:4 r input hsync high period measurement result: high byte[11:8] 3:0 r input vsync high period measurement result: high byte[11:8] address: 57 meas_hs_hi_l (hsync high period measured result) bit mode function 7:0 r input hsync high period measurement result: low byte[7:0] this result is expressed in terms of crystal clocks. when measured digitally, the result is expressed as the number of input clocks inside the input enable signal address: 58 meas_vs_hi_l (vsync high period measured result) bit mode function 7:0 r input vsync high period measurement result: low byte[7:0] this result is expressed in terms of input hs pulses address: 59 meas_active_region_h (active region measured by crstl_clk result) bit mode function 7:0 r/w active region measured by crystal clock 1 st read: measurement result: high byte[23:16] 2 nd read: measurement result: high byte[15:8] 3 rd read: measurement result: high byte[8:0] read pointer is auto increase, if write, the pointer is also reset to 1 st result. address: 5a clamp_start (clamp signal output start) default: 04h bit mode function 7:0 r/w start of output clamp signal pulse[7:0]: determine the number of input double-pixel between the trailing edge of input hsync and the start of the output clamp signal. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 70 address: 5b clamp_end (clamp signal output end) default: 10h bit mode function 7:0 r/w end of output clamp signal pulse[7:0]: determine the number of input double-pixel between the trailing edge of input hsync and the end of the output clamp signal. address: 5c clamp_ctrl0 default:00h bit mode function 7 r/w clamp mask enable 0: disable (disable) 1: enable 6 r/w clamp_trigger_edge_inverse 0: trailing edge (disable) 1: leading edge 5:0 r/w mask line number before devs [5:0] address: 5d clamp_ctrl1 default: 00h bit mode function 7 r/w sync processor test mode 0: normal (default) 1: enable test mode; (switch 70ns-ck to the time-out & polarity counters) 6 r/w select clamp mask as de vs 0: disable 1: enable 5:0 r/w mask line number after devs [5:0] cr5c[5:0] and cr5d[5:0] will set number of mask line before/after devs for coast, clamp mask, and cr5d[6]. macro vision address: 5e macro vision control default: 00h bit mode function 7:4 r/w skip line[3:0] skip lines after vsync detected 3 r/w test-mode for clamp, hs_raw is directly from pad 0: clamp source from normal hs 1: clamp source from hs_raw 2 r/w odd detection mode http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 71 0: line count (default) 1: vs position 1 r macrovision detected (on-line monitor) when detected macrovision occurred, this bit set to 1, else clear to 0. 0 r/w macro vision enable 0: disable (default) 1: enable highlight window address: 60 highlight window access port control default: 00h bit mode function 7 r/w enable highlight window access port 6 r/w enable highlight window 5:4 -- reserved 3:0 r/w highlight-window port address address: 61-00 highlight window horizontal start bit mode function 7:0 -- reserved 2:0 r/w highlight window horizontal start[10:8] address: 61-01 highlight window horizontal start bit mode function 7:0 r/w highlight window horizontal start[7:0] address: 61-02 highlight window horizontal end bit mode function 7:3 -- reserved 2:0 r/w highlight window horizontal end[10:8] address: 61-03 highlight window horizontal end bit mode function 7:0 r/w highlight window horizontal end[7:0] address: 61-04 highlight window vertical start http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 72 bit mode function 7:3 -- reserved 2:0 r/w highlight window vertical start[10:8] address: 61-05 highlight window vertical start bit mode function 7:0 r/w highlight window vertical start[7:0] address: 61-06 highlight window vertical end bit mode function 7:3 -- reserved 2:0 r/w highlight window vertical end[10:8] address: 61-07 highlight window vertical end bit mode function 7:0 r/w highlight window vertical end[7:0] highlight window horizontal/vertical reference point is den (display background start). address: 61-08 highlight window border bit mode function 7:4 -- reserved 3:0 r/w highlight window border width address: 61-09 highlight window border color bit mode function 7:6 -- reserved 5:0 r/w highlight window border red color msb 6bit (red color 2-bit lsb = 00) address: 61-0a highlight window border color bit mode function 7:6 -- reserved 5:0 r/w highlight window border green color msb 6bit (green color 2-bit lsb = 00) address: 61-0b highlight window border color bit mode function 7:6 -- reserved 5:0 r/w highlight window border blue color msb 6bit (blue color 2-bit lsb = 00) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 73 address: 61-0c highlight window control default : 00h bit mode function 7:6 r/w contrast / brightness application control 00: set a used on full region 01: set b used inside highlight window 10: set a used outside highlight window 11: set a used outside highlight window, and set b used inside highlight window contrast (cr62[1]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[7:6]=00 || cr60[6]=0 set a set a 1 cr61-0c[7:6]=01 && cr60[6]=1 set b bypass 1 cr61-0c[7:6]=10 && cr60[6]=1 bypass set a 1 cr61-0c[7:6]=11 && cr60[6]=1 set b set a brightness (cr62[0]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[7:6]=00 || cr60[6]=0 set a set a 1 cr61-0c[7:6]=01 && cr60[6)=1 set b bypass 1 cr61-0c[7:6]=10 && cr60[6]=1 bypass set a 1 cr61-0c[7:6]=11 && cr60[6]=1 set b set a 5:4 r/w gamma application control 00 : gamma used on full region 01: gamma used inside window 10: gamma used outside window 11: reserved gamma (cr67[6]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[5:4]=00 || cr60[6]=0 gamma gamma 1 cr61-0c[5:4]=01 && cr60[6]=1 gamma bypass 1 cr61-0c[5:4]=10 && cr60[6]=1 bypass gamma 3:2 r/w srgb/dcc/icm application control http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 74 00 : srgb/dcc/icm used on full region 01: srgb/dcc/icm used inside window 10: srgb/dcc/icm used outside window 11: reserved srgb (cr62[2]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[3:2]=00 || cr60[6]=0 srgb srgb 1 cr61-0c[3:2]=01 && cr60[6]=1 srgb bypass 1 cr61-0c[3:2]=10 && cr60[6]=1 bypass srgb icm (cre0[7]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[3:2]=00 || cr60[6]=0 icm icm 1 cr61-0c[3:2]=01 && cr60[6]=1 icm bypass 1 cr61-0c[3:2]=10 && cr60[6]=1 bypass icm dcc (cre4[7]) application control inside window outside window 0 x bypass bypass 1 cr61-0c[3:2]=00 || cr60[6]=0 dcc dcc 1 cr61-0c[3:2]=01 && cr60[6]=1 dcc bypass 1 cr61-0c[3:2]=10 && cr60[6]=1 bypass dcc 1:0 -- reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 75 inside window left-top point = (horizontal start + border width, vertical start + border width) inside window right-bottom point = (horizontal end, vertical end) border window left-top point = (horizontal start, vertical start) border window right-bottom point = (horizontal end+ border width, vertical end + border width) border = border window C inside window outside window = screen C border window color processor control address: 62 color_ctrl (color control register) default: 00h bit mode function 7 -- reserved to 0 6 r/w srgb precision 0: normal (default) 1: 1 bit shift 5:3 r/w srgb coefficient write enable 000: disable 001: write r channel (rrh,rrl,rgh,rgl,rbh,rbl) (address reset to 0 when written) (horizontal start, vertical start) (horizontal end, vertical end) border width inside window border http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 76 010: write g channel (grh,gbl,ggh,ggl,gbh,gbl) (address reset to 0 when written) 011: write b channel (brh,brl,bgh,bgl,bbh,bbl) (address reset to 0 when written) 100: r offset 101: g offset 110: b offset 2 r/w enable srgb function 0: disable (default) 1: enable 1 r/w enable contrast function: 0: disable the coefficient (default) 1: enable the coefficient 0 r/w enable brightness function: 0: disable the coefficient (default) 1: enable the coefficient address: 63 srgb_access_port bit mode function 7:0 w srgb_coef[7:0] ? ? + + + ? ? + + + = ? ? boffset b goffset g roffset r bb bg br gb gg gr rb rg rr b g r 1 1 1 ' ' ' brightness coefficient: address: 64 contrast /brightness access port control default: 00h bit mode function 7 r/w enable contrast /brightness access port 6:4 -- reserved 3:0 r/w contrast /brightness port address access data port continuously will get address auto increase. address: 65-00 bri_red_coe (set a) bit mode function 7:0 r/w brightness red coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-01 bri_grn_coe (set a) bit mode function 7:0 r/w brightness green coefficient: valid range: http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 77 valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-02 bri_blu_coe (set a) bit mode function 7:0 r/w brightness blue coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-03 cts_red_coe (set a) bit mode function 7:0 r/w contrast red coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-04 cts_grn_coe (set a) bit mode function 7:0 r/w contrast green coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-05 cts_blu_coe (set a) bit mode function 7:0 r/w contrast blue coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-06 bri_red_coe (set b) bit mode function 7:0 r/w brightness red coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-07 bri_grn_coe (set b) bit mode function 7:0 r/w brightness green coefficient: valid range: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-08 bri_blu_coe (set b) bit mode function 7:0 r/w brightness blue coefficient: valid range: -128(00h) ~ 0(80h) ~ +127(ffh) address: 65-09 cts_red_coe (set b) bit mode function 7:0 r/w contrast red coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-0a cts_grn_coe (set b) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 78 bit mode function 7:0 r/w contrast green coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) address: 65-0b cts_blu_coe (set b) bit mode function 7:0 r/w contrast blue coefficient: valid range: 0(00h) ~ 1(80h) ~ 2(ffh) when highlight window is disable, coefficient set a is used. gamma control address: 66 gamma_port bit mode function 7:0 w access port for gamma correction table l the input data sequence is {g0[9:2]}, {g0[1:0], 1 b0, d0[4:0]}, {3 b0, d1[4:0]}; {g2[9:2]}, {g2[1:0], 1 b0, d2[4:0]}, {3 b0, d3[4:0]}; ; {g254[9:2]}, {g254[1:0] , 1 b0, d254[4:0]}, {3 b0, d255[4:0]} for full gamma table. l the input data sequence is {g0[9:2]}, {g0[1:0], 1 b0, d0[4:0]}, {g2[9:2]}, {g2[1:0] , 1 b0, d2[4:0]} , {g254[9:2]}, {g254[1:0] ,1 b0, d254[4:0] } for compact gamma table. l for compact gamma table, d1[4:0]=d0[4:0], d3[4:0]=d2[4:0], , d(2n+1)[4:0]=d(2n)[4:0]. l g(n) is 10bit gamma coefficient, and d(n) is g(n+1) C g(n) with 5bit. l if n is even, gamma-port output is g(n) + d(n)*(2bit lsb brightness output)/4. l if n is odd, gamma-port output is g(n-1) + d(n-1) + d(n)*(2bit lsb brightness output)/4. l gamma can be only accessed when dclk exists. l the latest stage of d[n] can t let gamma curve exceed 255. address: 67 gamma_ctrl default: 00h bit mode function 7 r/w enable access channels for gamma correction coefficient: 0: disable these channels (default) 1: enable these channels 6 r/w gamma table enable 0: by pass (default) 1: enable 5:4 r/w color channel of gamma table 00: red channel (default) 01: green channel 10: blue channel 11: red/green/blue channel (r/g/b gamma are the same) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 79 3:1 -- reserved to 0 0 r/w gamma access type 0: access compact gamma table (default) 1: access full gamma table l access gamma_access register will reset gamma_port index. address: 68 gamma_bist (color control register) default: 00h bit mode function 7 r/w test_mode 0: disable, dither_out = dither_result[9:2]; // truncate to integer number (default) 1: enable, dither_out = dither_result[7:0]; // propagate decimal part for test 6:4 -- reserved to 0 3:2 r/w gamma bist select 00: bist disable (default) 01: red lut 10: green lut 11: blue lut 1 r/w gamma bist_progress 0: bist is done (default) 1: bist is running 0 r gamma bist test result 0: sram fail 1: sram ok dithering control address: 69 dithering_sequence_table bit mode function 7:6 w dithering sequence table (sr3) 5:4 w dithering sequence table (sr2) 3:2 w dithering sequence table (sr1) 1:0 w dithering sequence table (sr0) l there are three set of dithering sequence table, each table contains 32 elements, s0, s1, , s31. each element has 2 bit to index one of 4 dithering table. l input data sequence is {sr3,sr2,sr1,sr0}, {sr7,sr6,sr5,sr4}, , {sr31,sr30,sr29,sr28}, {sg3,sg2,sg1,sg0}, , {sg31,sg30,sg29,sg28}, {sb3,sb2,sb1,sb0}, , {sb31,sb30,sb29,sb28} for red, green and blue channel. l r + (2r+1) * c choose sequence element, where r is row number / 2, and c is column number / 2. address: 6a dithering_table_access (dithering table access port) bit mode function 7:4 w access port for dithering table d00/d02/ d10/d12/d20/d22/d30/d32 3:0 w access port for dithering table d01/d03/ d11/d13/d21/d23/d31/d33 l red, green, blue each channel has 4 dithering table, each table is 2x2 elements, and one element has 4 bit for 10b/8b, the elements should fill 0 to 3, for 10b/6b, the elements should fill 0 to 15. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 80 l input data sequence is [dr00 dr01],[dr02,dr03], , [dr30,dr31],[dr32,dr33], [dg00,dg01],[dg02,dg03], , [dg30,dg31],[dg32,dg33], [db00,db01],[db02,db03], , [db30,db31],[db32,db33]. d00 d01 d10 d11 d20 d21 d30 d31 d02 d03 d12 d13 d22 d23 d32 d33 address: 6b dithering_ctrl default: 00h bit mode function 7 r/w enable access dithering sequence table 0: disable (default) 1: enable 6 r/w enable access dithering table 0: disable (default) 1: enable 5 r/w enable dithering function 0: disable (default) 1: enable 4 r/w temporal dithering 0: disable (default) 1: enable 3 r/w dithering table value sign 0: unsigned 1: signed (2 s complement) 2 r/w dithering mode 0: new (default) 1: old 1 r/w vertical frame modulation 0: disable (default) 1: enable 0 r/w horizontal frame modulation 0: disable (default) 1: enable l {dithering sequence + frame number (if temporal dithering)} mod 4 determine which dithering table to use http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 81 overlay/color palette/background color control address: 6c overlay_ctrl (overlay display control register) default: 00h bit mode function 7:6 -- reserved to 0 5 r/w background color access enable 0: disable(reset cr6d write pointer to r) 1: enable 4:2 r/w alpha blending level (also enable osd frame control register 0x003 byte 1[3:2] 000: disable (default) 001 ~111: 1/8~ 7/8 1 r/w overlay sampling mode select: 0: single pixel per clock (default) 1: dual pixels per clock (the osd will be zoomed 2x in horizontal scan line) 0 r/w overlay port enable: 0: disable (default) 1: enable turn off overlay enable and switch to background simultaneously when auto switch to background. address: 6d bgnd_color_ctrl default: 00h bit mode function 7:0 r/w background color rgb 8-bit value[7:0] l there are 3 bytes color select of background r, g, b, once we enable background color access channel(cr6c[5] and the continuous writing sequence is r/g/b address: 6e overlay_lut_addr (overlay lut address) default: 00h bit mode function 7 r/w enable overlay color plate access: 0: disable (default) 1: enable 6 r/w reserved to 0 5:0 r/w overlay 16x24 look-up-table write address [5:0] l auto-increment while every accessing overlay lut access port . address: 6f color_lut_port (lut access port) bit mode function 7:0 w color palette 16x24 look-up-table access port [7:0] l using this port to access overlay color plate which addressing by the above registers. l the writing sequence into lut is [r0, g0, b0, r1, g1, b1, r15, g15, and b15] and the address counter will http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 82 be automatic increment and circular from 0 to 47. image auto function address: 70 h_boundary_h bit mode function 7 -- reserved 6:4 r/w horizontal boundary start: high byte [10:8] 3:0 r/w horizontal boundary end: high byte [11:8] address: 71 h_boundary_sta_l bit mode function 7:0 r/w horizontal boundary start: low byte [7:0] address: 72 h_boundary_end_l bit mode function 7:0 r/w horizontal boundary end: low byte [7:0] address: 73 v_boundary_h bit mode function 7 -- reserved 6:4 r/w vertical boundary start: high byte [10:8] 3:0 r/w vertical boundary end: high byte [11:8] vertical boundary search should be limited by vertical boundary start. address: 74 v_boundary_sta_l bit mode function 7:0 r/w vertical boundary start: low byte [7:0] address: 75 v_boundary_end_l bit mode function 7:0 r/w vertical boundary end: low byte [7:0] address: 76 red_noise_margin (red noise margin register) bit mode function 7:2 r/w red pixel noise margin setting register 1:0 -- reserved to 0 address: 77 grn_noise_margin (green noise margin register) bit mode function 7:2 r/w green pixel noise margin setting register 1:0 -- reserved to 0 address: 78 blu_noise_margin (blue noise margin register) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 83 bit mode function 7:2 r/w blue pixel noise margin setting register 1:0 -- reserved to 0 address: 79 diff_threshold bit mode function 7:0 r/w difference threshold address: 7a auto_adj_ctrl0 default: 00h bit mode function 7 r/w field_select_enable: auto-function only active when even or odd field. 0: disable (default) 1: enable 6 r/w field_select: select even or odd field. active when field_select_enable . 0: active when odd signal is 0 (default) 1: active when odd signal is 1 5 r/w even or odd pixel be measured 0: even 1: odd 4 r/w measure only even or odd pixel enable 0: disable (default) 1: enable 3:2 r/w vertical boundary search: 00: 1 pixel over threshold (default) 01: 2 pixel over threshold 10: 4 pixel over threshold 11: 8 pixel over threshold 1:0 r/w color source select for detection: 00: b color (default) 01: g color 10: r color 11: all (when using all mode, the result sod value will be right shift 1 bit) measure all r/g/b can be done in three frames address: 7b hw_auto_phase_ctrl0 default: 00h bit mode function 7:3 r/w number of auto-phase step (valut+1) (how many times (steps reference cr7b[2:0]) jumps when using hardware auto) 2:0 r/w hardware auto phase step http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 84 000: step =1 (default) 001 step =2 010: step =4 011: step =8 1xx: step =16 address: 7c hw_auto_phase_ctrl1 default: 00h bit mode function 7 r/w hardware auto phase select trigger 0: ivs 1: vertical boundary end 6 r/w low pass filter (121-lpf) 0: disable (default) 1: enable 5:0 r/w initial phase of auto-phase (0~63) for high freq: the phase sequence is 0,1,2 ..,63 (default) for low freq: the phase sequence is 0,2,4,6,8 .,126 address: 7d auto_adj_ctrl1 default: 00h bit mode function 7 r/w measure digital enable info when boundary search active 0: normal boundary search (default) 1: digital enable info boundary search.(digital mode) 6 r/w hardware / software auto phase switch 0: software (default) 1: hardware 5 r/w color max or min measured select: 0: min color measured (only when balance-mode, result must be complemented) (default) 1: max color measured 4 r/w accumulation or compare mode 0: compare mode (default) 1: accumulation mode 3 r/w mode selection for sod 0: sod edge mode ( original type ii mode i) (default) 1: sod edge + pulse mode 2 -- reserved to 0 1 r/w function (phase/balance) selection 0: auto-balance (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 85 1: auto-phase 0 r/w start auto-function tracking function: 0: stop or finished (default) 1: start control table/ function sub-function cr7d.6 cr7d.5 cr7d.4 cr7d.3 cr7d.1 cr7c auto-balance max pixel x 1 0 0 0 x min pixel x 0 0 0 0 x auto-phase type mode1 1 1 1 0 1 th mode2 1 1 1 1 1 th accumulation all pixel 1 1 1 0 0 0 table 1 auto-tracking control table address: 7e ver_start_end_h (active region vertical start register) bit mode function 7:4 r active region vertical start measurement result: bit[11:8] 3:0 r active region vertical end measurement result: bit[11:8] address: 7f ver_start_l (active region vertical start register) bit mode function 7:0 r active region vertical start measurement result: bit[7:0] address: 80 ver_end_l (active region vertical end register) bit mode function 7:0 r active region vertical end measurement result: bit[7:0] address: 81 h_start_end_h (active region horizontal start register) bit mode function 7:4 r active region horizontal start measurement result: bit [11:8] 3:0 r active region horizontal end measurement result: bit[11:8] address: 82 h_start_l (active region horizontal start register) bit mode function 7:0 r active region horizontal start measurement result: bit[7:0] address: 83 h_end_l (active region horizontal end register) bit mode function 7:0 r active region horizontal end measurement result: bit[7:0] address: 84 auto_phase_3 (auto phase result byte3 register) bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 86 7:0 r auto phase measurement result: bit[31:24] address: 85 auto_phase_2 (auto phase result byte2 register) bit mode function 7:0 r auto phase measurement result: bit[23:16] address: 86 auto_phase_1 (auto phase result byte1 register) bit mode function 7:0 r auto phase measurement result: bit[15:8] address: 87 auto_phase_0 (auto phase result byte0 register) bit mode function 7:0 r auto phase measurement result: bit[7:0] the measured value of r or g or b color max or min. (auto-balance) address: 88 reserved to 0 video (color space conversion) address: 89 yuv2rgb_ctrl (yuv to rgb control register) default: 00h bit mode function 7:5 r/w yuv coefficient write enable: 000: h12 high byte 001: h12 low byte 010: h22 high byte 011: h22 low byte 100: h23 high byte 101: h23 low byte 110: h33 high byte 111: h33 low byte 4 -- reserved to 0 3 r/w enable yuv/rgb coefficient access: 0: disable 1: enable if this bit is set, the address of the data port will reset to original, and continuously writes 6 bytes 2 r/w cb cr clamp 0: bypass 1: cb-128, cr-128 1 r/w y gain/offset: 0 : bypass 1: (y-16)*1.164 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 87 0 r/w enable yuv to rgb conversion: 0: disable yuv-to-rgb conversion (default) 1: enable yuv-to-rgb conversion address: 8a yuv_rgb_coef_data bit mode function 7:0 w coef_data[7:0] yuv/rgb matrix ? ? - - - ? ? - - = ? ? 128 128 ) ( 16 33 0 ) 1 ( 164 . 1 23 22 ) 1 ( 164 . 1 0 12 ) 1 ( 164 . 1 cb cr ory y h or h h or h or b g r l h12: 11 bits, 1 bit integer and 10-bit fractional bits (default: 5_80h) l h22: 10 bits, all fractional bits (default: 1_40h) l h23: 9 bits, the msb mean 0.25 (default: 0_a0h) l h33: 12 bits, 2 bit integer and 10-bit fractional bits (default: 7_00h) l to fill h coefficients expressed by 2 s complement without signed bit. l h22 and h23 can t be 000h http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 88 embedded timing controller address: 8b tcon_addr _port default: 00h bit mode function 7:0 r/w address port for embedded tcon access address: 8c tcon_data _port default: 00h bit mode function 7:0 r/w data port for embedded tcon access address: 8c-00 tc_ctrl1 (timing controller control register1) default: 01h bit mode function 7 r/w enable timing controller function (global) 0: disable (default) 1: enable reset all tcon pins after enable tcon function is set and ties low. 6 r/w tcon [n] toggle function reset 0: not reset (default) 1: reset by dvs 5 r/w inactive period data controlled by internal tcon [13] 0: den (default) 1: tcon [13] 4 r/w tcon_hs compensation 0: real tcon_hs = tcon_hs-4, real tcon_hs = tcon_hs-4 1: real tcon_hs = tcon_hs-27, real tcon_hs = tcon_hs-27 if setting tcon_hs > dh_total, then setting tcon_hs must subtract dh_total. 3 r/w reserved to 0 2 r/w 6/8 bit rsds 0: 6-bit rsds panel 1: 8-bit rsds panel 1:0 r/w display port configuration: 00: ttl 01: hz (pin 61~82, 85~106) 10: lvds 11: rsds address: 8c-01 lvds location pin driving control default: 08h bit mode function 7 r/w 2 line sum of difference threshold 1 value: bit [8], ie:th1 (also refer to cr8c-03) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 89 6 r/w 2 line sum of difference threshold 2 value: bit [8], ie:th2 (also refer to cr8c-04) 5 r/w reserved to 0 4 r/w pin 41/42/43/44/45/48/49/50/51/110/113/114/115/118/119/120/121/122 drive current setting 0: 4ma 1: 6ma 3:2 r/w display port driving current control (rsds / lvds) pin 52~57, 61~70, 73~82, 85~94, 97~106, 111~112 00: 2.5ma 01: 3ma 10: 3.5ma 11: 4ma 1 r/w display port driving current control (ttl) pin 52~57, 61~70, 73~82, 85~94, 97~106, 111~112 0: 4ma 1: 6ma 0 r/w reserved to 0 address: 8c-02 rsds misc default: 00h bit mode function 7 r/w rsds data latch inverted 0: non-inverted 1: inverted 6:4 r/w rsds data latch delay 000: 0ns delay 001: 0.5ns delay 010: 1ns delay 011: 1.5ns delay 100: 2ns delay 101: 2.5ns delay 110: 3ns delay 111: 3.5ns delay 3 r/w reserved to 0 2 r/w rsds green / clock pair swap (also refer to cr29[6:4]) 0: no swap (default) 1: swap 1 r/w rsds high/low bit swap (data) (also refer to cr29[6:4]) 0: swap (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 90 1: no swap 0 r/w rsds differential pair pn swap (data) (also refer to cr29[6:4]) 0: no swap (default) 1: swap au 17" rsds panel pin order: b0b1b2 g0g1g2clk r0r1r2 qdi 17" rsds panel pin order: b2b1b0 g2g1g0clk r2r1r0 cmo 17" rsds panel pin order: b2b1b0 clkg2g1g0 r2r1r0 l total swap function: ? even/odd swap ? red/blue swap ? 8 bit msb/lsb swap ? 6 bit msb/lsb swap ? rsds high/low bit swap ? rsds p/n swap ? rsds green/clk swap l 6 bit msb/lsb swap g1 g2 g3 ck g3 g2 g1 ck l green/clk swap g1 g2 g3 ck ck g1 g2 g3 l 6 bit msb/lsb swap first, then green/clk swap g1 g2 g3 ck g3 g2 g1 ck ck g3 g2 g1 l 8 bit msb/lsb swap g0 g1 g2 g3 ck g3 g2 g1 g0 ck l green/clk swap g0 g1 g2 g3 ck ck g0 g1 g2 g3 l 8 bit msb/lsb swap first, then green/clk swap g0 g1 g2 g3 ck g3 g2 g1 g0 ck ck g3 g2 g1 g0 address: 8c-03 pixel threshold high value for smart polarity (th1) default: 00h bit mode function 7:0 r/w 2 line sum of difference threshold 1 value: bit [7:0], ie:th1 (also refer to cr8c-01[7]) address: 8c-04 pixel threshold low value for smart polarity (th2) default: 00h bit mode function 7:0 r/w 2 line sum of difference threshold 2 value: bit [7:0], ie:th2 (also refer to cr8c-01[6]) address: 8c-05 line threshold value for smart polarity default: 00h bit mode function 7 r/w measure dot pattern over threshold 1: run. auto: always measure (reference to cr05[5]) manual: start to measure, clear after finish 0: stop 6 r dot pattern sum of difference measure result 1: over threshold 0: under threshold 5 r/w anti-flicker auto-measure control http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 91 1: auto 0: manual 4:0 r/w over difference line threshold value: bit [4:0] rsds display data bus control address: 8c-06 rsds display data bus interleaving line buffer length high byte default: 00h bit mode function 7 r/w rsds type iii line buffer bist enable 0: disable 1: enable 6:5 r/w buffer sram selection 00: front even-sram 01: front odd-sram 10: back even-sram 11: back odd-sram 4 r/w bist test is running 0: stop 1: start 3 r/w bist test result 0: fail 1: ok 2 r/w display data bus interleaving enable 0: disable (default) 1: enable 1:0 r/w interleaving line buffer line buffer : high byte [9:8] address: 8c-07 rsds display data bus interleaving line buffer length low byte default: 00h bit mode function 7:0 r/w interleaving line buffer line buffer : low byte [7:0] tcon horizontal/vertical timing setting address: 8c-08 tcon [0]_vs_lsb (tcon [0] vertical start lsb register) bit mode function 7:0 w line number [7:0] at which tcon control generation begins address: 8c-09 tcon [0]_vs_msb (tcon [0] vertical start/end msb register) bit mode function 7:4 w line number [11:8] at which tcon control generation ends http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 92 3:0 w line number [11:8] at which tcon control generation begins address: 8c-0a tcon [0]_ve_lsb (tcon [0] vertical end lsb register) bit mode function 7:0 w line number [7:0] at which tcon control generation ends address: 8c-0b tcon [0]_hs_lsb (tcon [0] horizontal start lsb register) bit mode function 7:0 w pixel count [7:0] at which tcon goes active address: 8c-0c tcon [0]_hs_msb (tcon [0] horizontal start/end msb register) bit mode function 7:4 w pixel count [11:8] at which tcon goes inactive 3:0 w pixel count [11:8] at which tcon goes active to be triggered on rising edge of the dclk address: 8c-0d tcon [0]_he_lsb (tcon [0] horizontal end lsb register) bit mode function 7:0 w pixel count [7:0] at which tcon goes inactive if the register number is large than display format, the horizontal component is always on. real tcon_hs = tcon_hs-4, real tcon_hs = tcon_hs-4 address: 8c-0e tcon [0]_ctrl (tcon [0] control register) default: 00h bit mode function 7 r/w tcon [n] enabl e (local) 0: disable (tcon [n] output clamp to 0 ) (default) 1: enable 6 r/w polarity control 0: normal output (default) 1: inverted output 5:4 -- reserved to 0 3 r/w toggle circuit enable/disable 0: normal tcon output (default) 1: toggle circuit enable when using toggle circuit enable mode, the tcon[n] will be 1 clock earlier than tcon[n- 1] and then toggling together, finally output will be 1 clock delay comparing to toggling result. 2:0 r/w tcon [13:10] & tcon [7:4] (tcon combination select) tcon [13] has inactive data controller function. tcon [13]~[10] has dot masking function tcon [7] has flicking reduce function. 000: normal tcon output (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 93 001: select tcon [n] and with tcon [n-1] 010: select tcon [n] or with tcon [n-1] 011: select tcon [n] xor with tcon [n-1] 100: select tcon [n-1] rising edge as toggle trigger signal (when toggle enable) 101: select tcon [n-1] rising edge as toggle trigger signal, then and (when toggle enable) 110: select tcon [n-1] rising edge as toggle trigger signal, then or (when toggle enable) 111: select tcon [n] and tcon [n-1] on alternating frames. -------------------------------------------------------------------------------------------------------------------- tcon [9:8] (tcon combination select) 000: normal tcon output 001: select tcon [n] and with tcon [n-1] 010: select tcon [n] or with tcon [n-1] 011: select tcon [n] xor with tcon [n-1] 100: select tcon [n-1] rising edge as toggle trigger signal (when toggle enable) 101: select tcon [n-1] rising edge as toggle trigger signal, then and (when toggle enable) 110: select tcon [n-1] rising edge as toggle trigger signal, then or (when toggle enable) 111: select tcon [n] and tcon [n-1] reference odd signal as alternating frames. -------------------------------------------------------------------------------------------------------------------- tcon [3] (tcon combination select) 000: normal tcon output 001: select tcon [3] and with tcon [2] 010: select tcon [3] or with tcon [2] 011: select tcon [3] xor with tcon [2] 100: select tcon [2] rising edge as toggle trigger signal (when toggle enable) 101: select tcon [2] rising edge as toggle trigger signal, then and (when toggle enable) 110: select tcon [2] rising edge as toggle trigger signal, then or (when toggle enable) 111: select reset(odd=0) or set(odd=1) tcon [3] by dvs, when toggle function enable -------------------------------------------------------------------------------------------------------------------- tcon [2] (clock toggle function )//toggle function is inactive 00x: normal tcon output 010: select dclk/2 when tcon [2] is 0 011: select dclk/2 when tcon [2] is 1 100: select dclk/4 when tcon [2] is 0 101: select dclk/4 when tcon [2] is 1 110: select dclk/8 when tcon [2] is 0 111: select dclk/8 when tcon [2] is 1 -------------------------------------------------------------------------------------------------------------------- http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 94 tcon [1] xx0: normal tcon output xx1: reverse-control signal output -------------------------------------------------------------------------------------------------------------------- tcon [0] 00x: normal tcon output 010: even rev 18/24-bit function ( rev0 on tcon [0]) odd rev 18/24-bit function ( rev1 on tcon [1]) 011: all rev 36/48-bit function ( rev on tcon [0], can also on tcon [1]) 100: even data output inversion controlled by tcon [0] is 0 odd data output inversion controlled by tcon [1] is 0 101: even data output inversion controlled by tcon [0] is 1 odd data output inversion controlled by tcon [1] is 1 dot masking address: 8c-5f/67/6f/77 tc_dot_masking_ctrl default: 00h bit mode function 7:3 r/w reserved to 0 2 r/w red dot masking enable 0: disable (default) 1: enable 1 r/w green dot masking enable 0: disable (default) 1: enable 0 r/w blue dot masking enable 0: disable (default) 1: enable when applying dot masking, the timing setting for tcon will be real tcon_mask_sta = tcon_sta+2 real tcon_mask_end = tcon_end +2 tcon [0] ~ tcon [13] control registers address map address data(# bits) default 0a,09,08 tcon [0]_vs_reg (11) 0d,0c,0b tcon [0]_hs_reg (11) 0e tcon [0]_ctrl_reg 00 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 95 0f reserved 12,11,10 tcon [1]_vs_reg (11) 15,14,13 tcon [1]_hs_reg (11) 16 tcon [1]_ctrl_reg 00 17 reserved 1a,19,18 tcon [2]_vs_reg (11) 1d,1c,1b tcon [2]_hs_reg (11) 1e tcon [2]_ctrl_reg 00 1f reserved 22,21,20 tcon [3]_vs_reg (11) 25,24,23 tcon [3]_hs_reg (11) 26 tcon [3]_ctrl_reg 00 27 reserved 2a,29,28 tcon [4]_vs_reg (11) 2d,2c,2b tcon [4]_hs_reg (11) 2e tcon [4]_ctrl_reg 00 2f reserved 32,31,30 tcon [5]_vs_reg (11) 35,34,33 tcon [5]_hs_reg (11) 36 tcon [5]_ctrl_reg 00 37 reserved 3a,39,38 tcon [6]_vs_reg (11) 3d,3c,3b tcon [6]_hs_reg (11) 3e tcon [6]_ctrl_reg 00 3f reserved 42,41,40 tcon [7]_vs_reg (11) 45,44,43 tcon [7]_hs_reg (11) 46 tcon [7]_ctrl_reg 00 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 96 47 reserved 4a,49,48 tcon [8]_vs_reg (11) 4d,4c,4b tcon [8]_hs_reg (11) 4e tcon [8]_ctrl_reg 00 4f reserved 52,51,50 tcon [9]_vs_reg (11) 55,54,53 tcon [9]_hs_reg (11) 56 tcon [9]_ctrl_reg 00 57 reserved 5a,59,58 tcon [10]_vs_reg (11) 5d,5c,5b tcon [10]_hs_reg (11) 5e tcon [10]_ctrl_reg 00 5f tcon [10]_ctrl_reg 62,61,60 tcon [11]_vs_reg (11) 65,64,63 tcon [11]_hs_reg (11) 66 tcon [11]_ctrl_reg 00 67 tcon [11]_ctrl_reg 00 6a,69,68 tcon [12]_vs_reg (11) 6d,6c,6b tcon [12]_hs_reg (11) 6e tcon [12]_ctrl_reg 00 6f tcon [12]_ctrl_reg 00 72,71,70 tcon [13]_vs_reg (11) 75,74,73 tcon [13]_hs_reg (11) 76 tcon [13]_ctrl_reg 00 77 tcon [13]_ctrl_reg 00 control for lvds address: 8c-78 lvds_ctrl0 default: 00h bit mode function 7:6 -- reserved to 0 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 97 5 r/w power up lvds even-port 0: power down (default) 1: normal 4 r/w power up lvds odd-port 0: power down (default) 1: normal 3:2 r/w watch dog model 00: enable watch dog(default) 01: keep pll vco = 1v 1x: disable watch dog 1 reversed 0 r watch dog control flag 0: watch dog not active (default) 1: watch dog active, reset pll and set vco = 1v address: 8c-79 lvds_ctrl1 default: 14h bit mode function 7:6 r/w reserved to 0 5:3 r/w ststl [2:0]: select test attribute 000: wd 001: vcom 010: ib40u (default) 011: ibvocm 100: plltst-fbak 101: plltst-fin 110: lvtst-ckdin 111: lvtst-lvdsin[6] 2:0 r/w rsds / lvds output common mode (default: 100) address: 8c-7a lvds_ctrl2 default: 03h bit mode function 7:6 -- reserved to 0 5:4 -- reserved 3 r/w pll lock edge 0: positive 1: negative 2:0 r/w bias generator adjust (011) address: 8c-7b lvds_ctrl3 default: 1ch bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 98 7 r/w reserved to 0 6 r/w lvds mirror (pin 73~82, 85~94) 0: normal (txe3+, txe3-, txec+, txec-, txe2+, txe2-, txe1+, txe1-, txe0+, txe0- , txo3+, txo3-, txoc+, txoc-, txo2+, txo2-, txo1+, txo1-, txo0+, txo0-) 1: mirror (txo0+, txo0-, txo1+, txo1-, txo2+, txo2-, txoc+, txoc-, txo3+, txo3-, txe0+, txe0-, txe1+, txe1-, txe2+, txe2-, txec+, txec-, txe3+, txe3-) 5:3 r/w sil [2:0] : pll charge pump current (i=5ua+5ua*code) (default: 011) 2:1 r/w srl [1:0] : pll resistor (r=6k+2k*code) (default: 10) 0 r/w bmts : bit-mapping table select 0: table 1 (default) 1: table 2 tclk+ lvds bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 txe0 er1 er0 eg0 er5 er4 er3 er2 er1 er0 eg0 er5 txe1 eg2 eg1 eb1 eb0 eg5 eg4 eg3 eg2 eg1 eb1 eb0 txe2 eb3 eb2 den vs hs eb5 eb4 eb3 eb2 den*6 vs*5 txe3 er7 er6 rsv eb7 eb6 eg7 eg6 er7 er6 rsv*7 eb7 txo0 or1 or0 og0 or5 or4 or3 or2 or1 or0 og0 or5 txo1 og2 og1 ob1 ob0 og5 og4 og3 og2 og1 ob1 ob0 txo2 ob3 ob2 den vs hs ob5 ob4 ob3 ob2 den*2 vs*1 txo3 or7 or6 rsv ob7 ob6 og7 og6 or7 or6 rsv*3 ob7 table 1 bit-mapping 6bit(5~0)+2bit(7~6) tclk+ lvds bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 bit 5 txe0 er3 er2 eg2 er7 er6 er5 er4 er3 er2 eg2 er7 txe1 eg4 eg3 eb3 eb2 eg7 eg6 eg5 eg4 eg3 eb3 eb2 txe2 eb5 eb4 den vs hs eb7 eb6 eb5 eb4 den*6 vs*5 txe3 er1 er0 rsv eb1 eb0 eg1 eg0 er1 er0 rsv*7 eb1 txo0 or3 or2 og2 or7 or6 or5 or4 or3 or2 og2 or7 txo1 og4 og3 ob3 ob2 og7 og6 og5 og4 og3 ob3 ob2 txo2 ob5 ob4 den vs hs ob7 ob6 ob5 ob4 den*2 vs*1 txo3 or1 or0 rsv ob1 ob0 og1 og0 or1 or0 rsv*3 ob1 table 2 bit-mapping 6bit(7~2)+2bit(1~0) address: 8c-7c lvds_ctrl4 default: 80h bit mode function 7:6 r/w e_rsv : even port reserve signal select 11: always 1 10: always 0 01: tcon [11] 00: pwm_0 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 99 5:4 r/w e_den : even port data enable signal select 11: always 1 10: always 0 01: tcon [9] 00: dena 3:2 r/w e_vs : even port vs signal select 11: always 1 10: always 0 01: tcon [7] 00: dvs 1:0 r/w e_hs : even port hs signal select 11: always 1 10: always 0 01: tcon [5] 00: dhs address: 8c-7d lvds_ctrl5 default: 80h bit mode function 7:6 r/w o_rsv : odd port reserve signal select 11: always 1 10: always 0 01: tcon [13] 00: pwm_1 5:4 r/w o_den : odd port data enable signal select 11: always 1 10: always 0 01: tcon [9] 00: dena 3:2 r/w o_vs : odd port vs signal select 11: always 1 10: always 0 01: tcon [7] 00: dvs 1:0 r/w o_hs : odd port hs signal select 11: always 1 10: always 0 01: tcon [5] 00: dhs http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 100 pin share address: 8d pin share addr port default: 00h bit mode function 7:0 r/w address port for pin share control access address: 8e pin share data port default: 00h bit mode function 7:0 r/w data port for pin share control access address: 8e-00 pin_share_ctrl0 default: 00h bit mode function 7 r/w crystal out frequency (glitch free mux) (be not controlled by software reset) 0: f xtal / 2 1: f xtal 6:3 r/w reserved to 0 2 r/w pin 48 (only for power-on-latch pin 3 = 1; always normal output if power-on-latch pin 3 = 0) 0: v16_y7 (default) 1: normal output (refer to bit1~0) note: be rsds output if single-port 8-bit rsds without even-odd swap or dual-port 8-bit rsds. 1:0 r/w pin 48 (only for power-on-latch pin3 = 0 or bit2 = 1) 00: cout (default) 01: pwm1 10: dhs 11: tcon0 address: 8e-01 pin_share_ctrl1 default: 00h bit mode function 7:6 r/w pin 42 00: v16_den (default) 01: reserved 10: tcon5 11: tcon10 5 r/w reserved to 0 4 r/w pin 43 0: v16_odd (default) 1: tcon11 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 101 3:2 r/w pin 44 00: v16_hs (default) 01: reserved 10: tcon4 11: tcon8 1:0 r/w pin 45 00: v16_vs (default) 01: reserved 10: tcon3 11: tcon9 address: 8e-02 pin_share_ctrl2 default: 00h bit mode function 7:6 r/w pin 3 (power on latch for mcu location selection) 00: pwm0 (default) 01: tcon0 10: dvs 11: tcon3 5:4 r/w pin 4 00: pwm1 (default) 01: tcon1 10: dhs 11: tcon12 3 r/w pin 110 0: cout (default) 1: tcon13 2:0 r/w pin 111 000: v8_0 (default) 001: ared1 010: pwm1 011: tcon2 100: tcon7 101: reserved 110: reserved 111: reserved note: be rsds output if single-port 8-bit rsds with even-odd swap or dual-port 8-bit rsds. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 102 address: 8e-03 pin_share_ctrl3 default: 00h bit mode function 7 r/w pin 49, 52 ~57 0: v16_y6 ~ v16_y0 (default) 1: normal output(refer bit6~1) note: 1. mcu interface has highest priority. 2. pin 52~57 is rsds output if single-port 8-bit rsds without even-odd swap or dual-port 8-bit rsds. 6:5 r/w pin 49 (only for bit7 = 1) 00: tcon7 (default) 01: pwm2 10: dvs 11: tcon1 4 r/w pin 52, 53 (only for bit7 = 1) 0: tcon13, tcon7 (default) 1: dclk, den i.e. become sdio0/sdio1 if power on latch for parallel port and mcu 52~57 location. 3:2 r/w pin 54 (only for bit7 = 1) 00: tcon11 (default) 01: dhs 10: bgrn0 11: rsv i.e. become sdio2 if power on latch for parallel port and mcu 52~57 location. 1 r/w pin 55, 56, 57 (only for bit7 = 1) 0: tcon0, tcon12, tcon3 (default) 1: bgrn1, bred0, bred1 i.e. become sdio3/scsb/sclk if power on latch for mcu 52-57 location. 0 r/w pin 50, 51 0: ddcscl1, ddcsda1 (default) 1: tcon4, tcon9 address: 8e-04 pin_share_ctrl4 default: 00h bit mode function 7 -- reserved to 0 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 103 6 r/w pin 122 0: pwm0 (default) 1: tcon9 5:4 r/w pin 112, 113, 114 00: v8_1, v8_2, v8_3 (default) 01: ared0, agrn1, agrn0 10: pwm2, ddcscl2, ddcsda2 11: tcon10, tcon8, tcon5 note 1. become sdio0/sdio1/sdio2 if power on latch for parallel port and mcu 112~119 location. 2. pin 112 is rsds output if single-port 8-bit rsds with even-odd swap or dual-port 8-bit rsds. 3 r/w pin 115, 118, 119 0: v8_4, v8_5, v8_6 (default) 1: tcon9, tcon7, tcon3 i.e. become sdio3/scsb/sclk if power on latch for mcu 112~119 location. 2:0 r/w pin 120, 121 000: v8_7, vclk (default) 001: dclk, dena 010: ddcsda2, ddcscl2 011: tcon6, tcon4 100: tcon11, tcon4 101: reserved 110: reserved 111: reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 104 embedded osd address: 90 osd_addr_msb (osd address msb 8-bit) bit mode function 7:0 r/w osd msb 8-bit address address: 91 osd _addr_lsb (osd address lsb 8-bit) bit mode function 7:0 r/w osd lsb 8-bit address address: 92 osd_data_port (osd data port) bit mode function 7:0 w data port for embedded osd access refer to the embedded osd application note for the detailed. address: 93 osd_scramble default: 05h bit mode function 7 r/w bist start 0: stop (default) 1: start (auto clear) 6 r bist result 0: fail (default) 1: success 5 r mcu writes data when osd on status (queue 1 byte data) 0: mcu writes data to osd but not to real position (there is one level buffer here) 1: mcu doesn t write data, or data has been written to real position 4 r double_buffer_write_status 0: double buffer write out is finish, or data write to double buffer is not ready, or no double buffer function. 1: after data write to dbuf and before dbuf write out, such that double buffer is busy. 3 -- reserved to 0 2:0 r/w double buffer depth (default=6) 000~101=>1~6 address: 94 osd_test bit mode function 7:0 r/w testing pattern reset out and panel switch mos control address: 95 power_on_reset_regulator default: 14h bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 105 7:6 r/w negative threshold value for power on reset 00:1.8v(default) 01:2.0v 10:2.2v 11:2.4v 5:4 r/w negative threshold value for mcu power detecting 00: 1.2v 01: 1.3333v (default) 10: 1.4666v 11: 1.6v 3 -- reserved 2:0 r/w adc regulator voltage value[2:0] (supplying 200ma current) 000 to 111 => 2.2v to 1.5v (default 100=>1.8v) address: 96 ebd_reglator_vol default: 88h bit mode function 7:5 r/w digital core regulator voltage value[2:0] (supplying 200ma current) 000 to 111 => 2.2v to 1.5v (default 100=>1.8v) 4:3 r/w band-gap voltage of regulator adjust default: 01 2 r/w reserved to 0 1 r/w panel switch ( only for 3.3v) 0: switch off (default) 1: switch on 0 -- reserved to 0 schmitt trigger control address: 97 hs_schmitt_trigge_ctrl default: 41h bit mode function 7 r/w hsync schmitt power down (only for schmitt trigger new mode) 0: power down (default) 1: normal 6 r/w polarity select 0: negative hsync (high level) 1: positive hsync (low level) (default) 5 r/w schmitt trigger mode 0: old mode (default) 1: new mode http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 106 4 r/w threshold voltage fine tune (only for schmitt trigger new mode) 0: 0v (default) 1: -0.1v 3:2 r/w positive threshold voltage 1:0 r/w negative threshold voltage l there are 3 mode of the hsync schmitt trigger. 1. old mode 1: original hsync schmitt trigger. bit[6:5]=00 v t + = 1.5v, v t - = 1.0v 2. old mode 2: the easy hsync schmitt trigger. bit[6:5]=10 bit[1:0] v t + v t - 01 2.0v 1.5v 11 1.5v 1.0v 3. new mode: fully programmable schmitt trigger. the following table will determine the schmitt trigger positive and negative voltage: bit[6]=1 (positive hsync) bit[6] = 0 (negative hsync) bit[3:2] v t + bit[1:0] v t - bit[3:2] v t + bit[1:0] v t - 00 1.4v 00 v t + - 1.2v 00 1.8v 00 v t + - 1.2v 01 1.6v 01 v t + - 1.0v 01 2.0v 01 v t + - 1.0v 10 1.8v 10 v t + - 0.8v 10 2.2v 10 v t + - 0.8v 11 2.0v 11 v t + - 0.6v 11 2.4v 11 v t + - 0.6v l after we get the threshold voltage by the table, we still can fine tune it: final positive threshold voltage = v t + - 0.1* bit[4] final negative threshold voltage = v t - - 0.1* bit[4] http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 107 phase-lock-loop (pll) dds setting for adc address: 98 pll_div_ctrl default: 04h bit mode function 7 r/w pfd selection 0: new pfd fine (default) 1: new pfd coarse ( the resolution will be 1/2 of the pfd fine mode) 6 r/w dds tracking edge 0: hs positive edge (default) 1: hs negative edge 5 r/w dds reset enable 0: normal function (default) 1: dds circuit s reset will be asserted, for test only 4 r/w test mode : (for production test) 0: normal (default) 1: test mode 3 r/w hs output synchronized by 0: phase 32 1: phase 0 (default) 2:1 r/w delay compensation mode 00: mode 0 01: mode 1 10: mode 2 (default) 11: mode 3 0 r/w clock select for div 0: phase 0 (phase-0 of pll2) (default) 1: internal clk (fav) address: 99 i_code_l default: 47h bit mode function 7:3 r/w old/new mode: i_code [9:5] (default: 01000) 2 r/w old mode: i_code [4] (default=1) new mode: i-code control mechanism 0: new linear mode, pe*(2+new_i[13]) 1: old mode, p-code = i[17:0] C 1 (default) 1:0 r/w old mode: i_code [3:2] (default: 11) new mode : p-code protection mode 00 => no protection 01 => 1 bit protection 10 => 2 bits protection 11 => 3 bits protection (default) address: 9a i_code_m default: 00h bit mode function 7:6 r/w old mode : i_code [15:14] (default: 00) 5 r/w old mode : i_code [13] (default:0) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 108 new mode : i_code calibrated setting 4 r/w old mode : i_code [12] (default:0) new mode : p_code calibrated setting 3 r/w old mode : i_code [11] 2 r/w i_code [10] or pfd type selection 0: old pfd (default) 1: new pfd 1 r/w old mode : i_code [1] (default: 0) new mode : p-code mapping curve 0: choose the new p-code mapping curve (pe*2+new_i[12])* 2 _ 2 + p new 1: choose the old p-code mapping curve 0 r/w old mode: i_code [0] (default: 0) new mode: i-code multiplication factor 0: choose the new i-code multiplication factor = ) 2 ] 5 : 9 [ _ ( 2 + i new 1: choose the old i-code multiplication factor i control =( i-code control mechanism)*(i-code multiplication factor) address: 9b p_code default: 18h bit mode function 7 r/w phase swallow down enable 0: swallow up (default) 1: swallow down 6:5 r/w i_code[17:16] default: 00b 4:0 r/w p_code[4:0] default: 18h address: 9c pfd_calibrated_results default: 8 b 00xxxxxx bit mode function 7 -- reserved to 0 6 r/w pfd calibration enable overwrite 0 to 1 return a new pfd calibrated value. 5:0 r pfd calibrated results[5:0] address: 9d pe_mearsure default: 00h bit mode function 7:6 -- reserved to 0 5 r/w pe measure enable 0: disable (default) 1: start pe measurement, clear after finish. 4:0 r pe value result [4:0] address: 9e pe_max_measure default: 00h http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 109 bit mode function 7 --- reserved to 0 6 r/w pe max. measure enable 0: disable (default) 1: start pe max. measurement 5 r/w pe max. measure clear 0: clear after finish (default) 1: write 1 to clear pe max. value 4:0 r pe max value[4:0] address: 9f fast_pll_ctrl default: 00h bit mode function 7 -- reserved to 0 6 r/w enable apll setting 0: disable (default) 1: enable (auto clear when finished) when cr9f[5] enabled, enable this bit will write pll2m/n, plldiv and dds sum_i at the end of input vertical data enable 5 r/w enable fast pll mechanism 0: disable (default) 1: enable 4 -- reserved to 0 3 r/w dds i_sum setting updated enable 0: disable (default) 1: enable (auto clear when finished) 2 r/w measure i_sum 0: disable 1: enable (auto clear after finish) 1 r/w enable port a0 0: disable port a0 access 1: enable port a0 access when this bit is 0, port address will be reset to 00, and will auto increase when read or write 0 r/w select i_sum for read 0: select sum_i_pre [32:1] for read 1: select sum_i_now [32:1] for read address: a0 fast_pll_isum bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 110 7:0 r/w i_sum (auto increase) 1 st i_sum[31:24] 2 nd i_sum[23:16] 3 rd i_sum[15:8] 4 th i_sum[7:0] adc pll1 address: a1 pll1_m (m parameter register) default: 0fh bit mode function 7:0 r/w pll1m[7:0] (pll1 dpm value C 2) address: a2 pll1_n (n parameter register) default: 80h bit mode function 7 r/w pll1pwdn (pll1 power down) 0: normal run 1: power down (default) 6:4 --- reserved to 0 3:0 r/w pll1n[3:0] (pll1 dpn value C 2) l pll1_n modify to only 4-bit. l assume pll1_m=0x0b, p1m=0x0b+2=13; pll1_n=0x03, p1n=0x03+2=5; f_in = 24.576mhz. f_pll1 = f_in x p1m / p1n = 24.576 x 13 / 5 = 63.8976mhz l if the target frequency is f_adc, the constraint of f_pll1 is (15/16)*f_adc < f_pll1 < f_adc address: a3 pll1_crnt (pll1 current/resistor register) default: 33h bit mode function 7 r/w reserved to 0 6:4 r/w pll1vr[2:0] (pll1 loop filter resister control) 000: 20k 001: 21k 010: 22k 011: 23k (default) 100: 24k 101: 25k 110: 26k 111: 27k 3:0 r/w pll1si[3:0] (pll1 charger pump current ichdpll) (default: 0011b) icp = 2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]+20ua*bit[3] l keep icp/dpm constant address: a4 pll1_wd (pll1 watch dog register) default: 0eh http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 111 bit mode function 7 r pll1status (pll1 wd status) 0: normal (default) 1: abnormal 6 r/w pll1wdrst (pll1 wd reset) 0: normal (default) 1: reset 5 r/w pll1wdset (pll1 wd set) 0: normal (default) 1: set 4:3 r/w pll1wdvset[1:0] (pll1 wd voltage set) 00: 2.46v 01: 1.92v(default) 10: 1.36v 11: 1.00v 2 r/w pll1updn (pll1 frequency tuning up/down) 0: freq down 1: freq up (default) 1 r/w pll1msbstop (pll1 frequency tuning enable) 0: disable 1: enable (default) 0 --- reserved to 0 adc pll2 address: a5 pll2_m (m parameter register) default: 3eh bit mode function 7:0 r/w pll2_m[7:0] (pll2 dpm value C 2) (default 3e) address: a6 pll2_n (n parameter register) default: 3dh bit mode function 7:0 r/w pll2_n[7:0] (pll2 dpn value C 2) (default 3d) l assume pll2_m=0x0a, p2m=0x0a+2=12; pll2_n=0x04, p2n=0x04+2=6; f_in =65 mhz . l f_pll2 = f_in x p2m x 2 / p2n /2 = 65 x 12 x 2 / 6 / 2 = 130 mhz l the constraint of f_pll2 is that p2n =(int)(f_in / 10) address: a7 pll2_crnt (pll2 current/resistor control) default: 6fh bit mode function 7:5 r/w pll2vr[2:0] (pll2 loop filter resister control) 000: 15k 001: 16k http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 112 010: 17k 011: 18k 100: 19k 101: 20k 110: 21k 111: 22k 4:0 r/w pll2si[4:0] (pll2 charger pump current ichdpll) icp = 2.5ua+2.5ua*bit[0]+5ua*bit[1]+10ua*bit[2]+20ua*bit[3]+30ua*bit[4] l keep icp/dpm constant address: a8 pll2_wd (pll2 watch dog register) default: 09h bit mode function 7 r pll2status (pll2 wd status) 0: normal (default) 1: abnormal 6 r/w pll2wdrst (pll2 wd reset) 0: normal (default) 1: reset 5 r/w pll2wdset (pll2 wd set) 0: normal (default) 1: set 4:3 r/w pll2wdvset[1:0] (pll2 wd voltage set) 00: 2.46v 01: 1.92v(default) 10: 1.36v 11: 1.00v 2:1 r/w adckmode[1:0] (adc input clock select mode) 00 : single clock mode (default) 01 : single inverse-clock mode 10 : external clock mode 11 : dual clock mode (1x and 2x clock) 0 r/w pll2pwdn (pll2 power down) 0: normal run 1: power down (default) address: a9 plldiv_h default: 05h bit mode function 7 --- reserved to 0 6 r/w phase_select_method http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 113 0: manual (default) 1: look-up-table 5 r/w pll2ph0path 0: short path (default) 1: long path (compensate pll_adc path delay) 4 r/w pll2d2 0:adc clk=1/2 vco clk (default) 1:adc clk=1/4 vco clk 3:0 r/w pll divider ratio control. high-byte [11:8]. (default: 5h) address: aa plldiv_l default: 3fh bit mode function 7:0 r/w pll divider ratio control . low-byte [7:0] . plldiv should be double buffered when plldiv_lo changes and iden_stop occurs. l this register determines the number of output pixel per horizontal line. pll derives the sampling clock and data output clock (dclk) from input hsync. the real operation divider ratio = plldiv+1 l the power up default value of plldiv is 053fh(=1343, vesa timing standard, 1024x768 60hz, horizontal time). l the setting of plldiv must include sync, back-porch, left border, active, right border, and front-porch times. l control-register a9 & aa will filled in when control-register aa is written. address: ab pllphase_ctrl0 (select phase to a/d) default: 30h bit mode function 7 r/w pll2d2x control (default=0) 6 r/w pll2d2y control (default=0) 5 r/w pll2x (pll2 x phase control) (default=1) 4 r/w pll2y (pll2 x phase control) (default=1) 3:0 r/w pll2sck[4:1] (pll2 32 phase pre-select control) (default=0h) address: ac pllphase_ctrl1 (select phase to a/d) default: 00h bit mode function 7 r/w pll2sck[0] (pll2 32 phase pre-select control) (default=0) 6 r/w msb of 128 phase (only for adc clk=1/4 vco clk) (default=0) 5:0 r/w phase select the index of look-up-table[5:0] (default=0) l when phase_select_method=1, phase is selected by cr[ac]-bit[6:0]. l when phase_select_method=0, pll2d2x, pll2d2y, pll2x, pll2y, pll2sclk[4:0] should be double buffered when pll2sck[0] is updated address: ad pll2_phase_interpolation default: 50h bit mode function 7:6 r/w pll2 phase interpolation control load (default: 01) 5:3 r/w pll2 phase interpolation control source (default: 010) 2:1 r/w pll2 add phase delay http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 114 00: original phase selected by x,y and 16-phase pre-select 01-11: add 1-3 delay to original phase selected by x,y and 32-phase pre-select 0 r/w reserved to 0 phase [xy^^^^^] phase [xy ^^^^^] phase [xy ^^^^^] phase [xy ^^^^^] 0 [11 00000] 16 [01 10000 ] 32 [10 00000] 48 [00 10000] 1 [11 00001] 17 [01 10001 ] 33 [10 00001] 49 [00 10001] 2 [11 00010] 18 [01 10010 ] 34 [10 00010] 50 [00 10010] 3 [11 00011] 19 [01 10011] 35 [10 00011] 51 [00 10011] 4 [11 00100] 20 [01 10100] 36 [10 00100] 52 [00 10100] 5 [11 00101] 21 [00 10101] 37 [10 00101] 53 [00 10101] 6 [11 00110] 22 [00 10110] 38 [10 00110] 54 [00 10110] 7 [11 00111] 23 [01 10111] 39 [10 00111] 55 [00 10111] 8 [11 01000] 24 [01 11000] 40 [10 01000] 56 [00 11000] 9 [11 01001] 25 [01 11001] 41 [10 01001] 57 [00 11001] 10 [01 01010] 26 [10 11010] 42 [10 01010] 58 [11 11010] 11 [01 01011] 27 [10 11011] 43 [10 01011] 59 [11 11011] 12 [01 01100] 28 [10 11100] 44 [00 01100] 60 [11 11100] 13 [01 01101] 29 [10 11101] 45 [00 01101] 61 [11 11101] 14 [01 01110] 30 [10 11110] 46 [00 01110] 62 [11 11110] 15 [01 01111] 31 [10 11111] 47 [00 01111] 63 [11 11111] display pll address: ae dpll_m (dpll m divider register) default: 2ch bit mode function 7:0 r/w dpllm[7:0] (dpll dpm value C 2) address: af dpll_n (dpll n divider register) default: 83h bit mode function 7 r/w dpllpwdn (dpll power down) 0: normal run 1: power down (default) 6 r/w dpllfreeze (dpll output freeze) 0: normal (default) 1: freeze 5:4 r/w dpllo[1:0] (dpll output divider) 00: div1 (default) 01: div2 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 115 10: div4 11: div8 3:0 r/w dplln[7:0] (dpll dpn value C 2) (default: 3h) l assume dpll_m=0x7d, dpm=0x7d+2=127; dpll_n=0x0a, dpn=0x0a+2=12; divider=1/4, f_in = 24.576mhz. f_dpll = f_in x dpm / dpn x divider = 24.576 x 127 / 12 / 4 = 65.024mhz. l if lpf_mode = 1, suppose dpm=110, dpn = 12, ich = idch[000100] = 6.25ua, dpll=225mhz, then dpm / ich =17.6. please keep the ratio as constant. l if lpf_mode = 0, suppose dpm=46, dpn = 5, ich = idch [101010] =27.5ua, dpll=226mhz, then dpm / ich = 1.67. please keep the ratio as constant. address: b0 dpll_crnt (dpll current/resistor register) default: c8h bit mode function 7:6 r/w dpllvr[1:0] (dpll loop filter resister control) 00: 16k (lpf mode = 0), 46k (lpf mode = 1) 01: 18k (lpf mode = 0), 53k (lpf mode = 1) 10: 20k (lpf mode = 0), 60k (lpf mode = 1) 11: 22k (lpf mode = 0), 67k (lpf mode = 1) (default) 5:4 reserved 3:0 r/w dpllsi[3:0] (dpll charger pump current ichdpll) (default: 1000) icp=(1ua+1ua*bit[0]+2ua*bit[1]+4ua*bit[2]+8ua*bit[3]) l keep icp/dpm constant address: b1 dpll_wd (watch dog register) default: 16h bit mode function 7 r dpllstatus (dpll wd status) 0: normal 1: abnormal 6 r/w dpllwdrst (dpll wd reset) 0: normal (default) 1: reset 5 r/w dpllwdset (dpll wd set) 0: normal (default) 1: set 4:3 r/w dpllwdvset[1:0] (dpll wd voltage set) 00: 0.58v 01: 0.74v 10: 0.88v (default) 11: 1.17v 2 r/w dpllupdn (dpll frequency tuning up/down) 0: freq up 1: freq down (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 116 1 r/w dpllstop (dpll frequency tuning enable) 0: disable 1: enable (default) turn on before crbb[0]. 0 r/w dplllpfmode (dpll lpf mode) 0: dpn<=5 lpfmode=0 ich=9.15ua dpm=46 dpn=5 (default) 1: 16>=dpn>=5 lpfmode=1 ich=3.2ua dpm=110 dpn=12 address: b2 dpll other default: 04h bit mode function 7:5 -- reserved 4 r/w dpll clock to sscg 0: dpllvco/4 (defalult) 1: ( dpllvco+phase_swallow )/4 3 r/w dpll reference frequency select 0: original crystal clock (default) 1: clock after m2pll 2 r/w dpll vco ron (increase vco_op phase margin) 0: disable 1: enable (default) 1 r/w dpll vco start (startup vco) 0: disable (default) 1: enable 0 r/w dpll bpn (dpll dividend enable) 0: dpll_n dividend enable 1: n dividend disable multiply pll for input cyrstal address: b3 m2pll_addr_port bit mode function 7:3 -- reserved 2:0 r/w address for m2pll access address: b4 m2pll_data _port bit mode function 7:0 r/w data port for m2pll address: b4-00 multi_pll_ctrl0 default: 92h http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 117 bit mode function 7:3 r/w m2pll m code[4:0]-2 (dpm) (shall not be 0) default = 20 => 10010 2 r/w m2pll power down 0: normal run (default) 1: power down 1 r/w m2pll n code 0: n=1 1: n=2 (default) 0 r/w reserved to 0 vco range = 120mhz ~ 250mhz fif0_ clock = f xtal _ * m2pll_m / m2pll_n por clock = f xtal * m2pll_m / m2pll_n / 8 address: b4-01 multi_pll_ctrl1 default: 94h bit mode function 7:6 r/w m2pll loop filter resistor control 00: 15k 01: 18k 10: 21k(default) 11: 24k 5:4 r/w m2pll loop filter charge current control(default:01) icp=5ua+5ua*bit[4]+10ua*bit[5] i.e.: keep icp/dpm constant 3:2 r/w m2pll wd voltage 00: 0.80v 01: 1.0v (default) 10: 1.2v 11: 1.4v 1 r/w m2pll_wdrst 0: normal (default) 1: reset ( m2pll function as a normal pll, regardless wd) 0 r/w m2pll_wdset 0: normal (default) 1: set (free run by wd asserts vco voltage) address: b4-02 multi_pll_ctrl1 default: 40h bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 118 7 r m2pll wd status 0: normal 1: abnormal 6 r/w m2pll output freeze (fifo clock) 0: normal (default) 1: freeze i.e.: when output is frozen, the internal pll is still operating 5:0 -- reserved crb4-00~02 are not controlled by software reset. pll test address: b4-03 pll_test (pin3) default: 19h bit mode function 7:6 -- reserved to 0 5 r/w pll_tp1_fast (pll_testpin1 ttl output driving) 0: slow (default) 1: fast 4:3 r/w pll_tp1_mode[1:0] (pll_testpin1 i/o mode select) 00: analog in/out 01: open drain output 10: digital ttl output 11: digital ttl input (3v) power on latch to determine mcu direction (default) 2:0 r/w pll_tp1_mux[2:0] (pll_testpin1 output signal select) 000: dpll clock 001: pll1 status 010: fav clock(from pll1) 011: pll2 status 100: hsout 101: adc clock (from pll2) 110: empty flag(ddc/ci buffer) 111: normal operation usage (refer to pin share control) address: b4-04 pll_test (pin4) default: 19h bit mode function 7 -- reserved to 0 6 r/w select the external clock source instead of dpll clock for mp test (digital ttl input) 0: disable 1: enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 119 5 r/w pll_tp2_fast (pll_testpin1 ttl output driving) 0: slow 1: fast 4:3 r/w pll_tp2_mode[1:0] (pll_testpin2 i/o mode select) 00: analog in/out 01: open drain output 10: digital ttl output 11: digital ttl input (3v) (default) 2:0 r/w pll_tp2_mux[2:0] (pll_testpin2 output signal select) 000: pll1 clock 001: dpll status 010: pll2 phase0 clock 011: m2pll clock 100: hsfb 101: normal operation usage (refer to pin share control) 110: full flag(ddc/ci buffer) 111: dclk/4 dclk spread spectrum address: b5 dclk_fine_tune_offset_msb default: 00h bit mode function 7:6 -- reserved 5 r/w only even / odd field mode enable 0: disable (default) 1: enable 4 r/w even / odd field select 0: even (default) 1: odd 3:0 r/w dclk offset [11:8] in fixed last line dvtotal & dhtotal address: b6 dclk_fine_tune_offset_lsb default: 00h bit mode function 7:0 r/w dclk offset [7:0] in fixed last line dvtotal & dhtotal address: b7 spread_spectrum default: 00h bit mode function 7:4 r/w dclk spreading range (0.0~7.5%) the bigger setting, the spreading range will bigger, but not uniform http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 120 3 r/w spread spectrum fmdiv (ssp_fmdiv)//(0) 0: 33k 1: 66k 2 r/w spread spectrum setting ready for writing (auto clear) 0: not ready 1: ready to write 1:0 r/w frequency synthesis select (f & f-n*df) 00~11: n=1~4 l the spread spectrum setting ready for writing means 4 kinds of registers will be set after this bit is set: 1. dclk spreading range 2. spread spectrum fmdiv 3. dclk offset setting 4. frequency synthesis select address: b8 fixed_last_line_msb bit mode function 6:4 r/w fixed last line length [11:8] 3:0 r/w fixed dvtotal [11:8] address: b9 fixed_last_line_dvtotal _lsb bit mode function 7:0 r/w fixed dvtotal [7:0] address: ba fixed_last_line_ length_lsb bit mode function 7:0 r/w fixed last line length [7:0] l fixed last line value can t be zero, and can t smaller than dh_sync width. address: bb fixed_last_line_ctrl default: 00h 7:4 -- reserved to 0 3 r/w enable new design function in fixed last line mode 0: disable (default) 1: enable 2 r/w dds spread spectrum test enable 0: disable (default) 1: enable 1 r/w enable the fixed dvtotal & last line dhtotal function 0: disable (default) 1: enable 0 r/w enable dds spread spectrum output function 0: disable (default) 1: enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 121 procedure: l first, we have set m/n code and then we need to tune dclk offset to achieve frame-sync, every step of offset frequency is dclk/ 15 2 . l when we finished the frame-sync, we turn on cr bb[1] to let the system running in to free-run mode, at this time, the crb8,crb9,crba are the reference dv and dh total and fixed last line length. l but the free-run mode dvs should be close to frame-sync mode dvs to achieve pseudo-frame-sync( actually, it is free run mode now) l then we use crb7 [1:0] (f-n*df) to keep dvs and dvs very closely to achieve pseudo-frame-sync. notice: l in rtd2523, when all the setting above is ready, then we open spread spectrum function, the dclk offset will shift, please keep the dclk offset keeps steady when we open spread spectrum function. l in real free-run mode, the dv_total refers to cr32/cr33, and in fixed-last-line mode, the free-run timing dv_total refers to crb8/crb9, at this time cr35/36 serve for vsync-timeout watch dog reference. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 122 embedded tmds address: bc tmds_measure_select default: 00h bit mode function 7 r/w transition measurement method 0: measure the number of transition for n-clock duration (crbc[3:0]) 1: measure the number of transition smaller than 16/64 clock period (crbd[0]) for 1-frame duration 6:4 r/w measure times(exponential of 2) 000: 1 001: 2 010: 4 011: 8 100: 16 101: not available 110: not available 111: not available 3:0 r/w numbers of clock period, measurement duration (where clock frequency is 12khz) 0000: 16 0001: 1 0010: 2 0011: 3 . 1111: 15 this function will do bit [6:4] times, each time lasts for bit [3:0]/12 ms. address: bd tmds_meas_result0 default: 0000_0110b bit mode function 7 r/w transition measurement 0:stop measure, cleared after finish (default) 1:start measure 6:5 r/w measure result select 00: ave value (default) 01: max value 10: min value 4:3 r/w measure select 00: measure hsync transition times before error correction. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 123 01: measure hsync transition times after error correction. 10: measure data enable transition times before error correction. 11: measure data enable transition times after error correction. 2 r/w clock dc offset 0: disable 1: enable dc offset compensation 1 r/w r/g/b dc offset 0: disable 1: enable dc offset compensation 0 r/w criterion of transition count, duration smaller than 0: 16 clock 1: 64 clock address: be tmds_meas_result1 bit mode function 7 --- reserved 6:0 r value of measure result [6:0] (item refer to crbd[6:5]) address: bf tmds_ctrl bit mode function 7 r b channel detect (de low 128 clock)(write clear) 0: no 1: yes 6 r g channel detect (de low 128 clock)(write clear) 0: no 1: yes 5 r r channel detect (de low 128 clock)(write clear) 0: no 1: yes 4 r hsync occur(write clear) 0: no 1: yes 3 r vsync occur(write clear) 0: no 1: yes 2:0 reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 124 error correction hs_dec vs_dec hs' vs' m u x hs_gen vs_gen h/v occur flag de_only address: c0 crc_output_byte_2 bit mode function 7:0 r/w 1 st read=> output crc-24 bit 23~16 2 nd read=> output crc-24 bit 15~8 3 rd read=> out put crc-24 bit 7~0 l the read pointer should be reset when 1. crc output byte is written 2. crc check starts. l the read back crc value address should be auto-increase, the sequence is shown above address: c1 tmds_output_ctrl default: 00 h bit mode function 7 r/w auto output enable 0: disable (default) 1: enable 6 r/w tmds r channel output enable 0: disable (default) 1: enable 5: r/w tmds g channel output enable 0: disable (default) 1: enable 4 r/w tmds b channel output enable 0: disable (default) 1: enable 3 r/w oclk enable 0: disable (default) 1: enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 125 2 r/w oclk invert enable 0: normal (default) 1: enable 1 r/w reserved 0 r/w clk25xinv 0: no invert (default) 1: invert address: c2 power_on_off_ctrl default: 20h bit mode function 7 r/w de-only: generate vs/hs from de signal 0: disable (default) 1: enable 6 r/w b/r channel swap 0: no swap (default) 1: swap 5 r/w input channel control by auto function 0: manual 1: auto (default) 4 r/w enable clock channel: turn on clock channel pll (for manual use) 0: disable (default) 1: enable 3 r/w enable red input port (for manual use, cut off 50ohm internal resistor) 0: disable (default) 1: enable 2 r/w enable green input port (for manual use, cut off 50ohm internal resistor) 0: disable (default) 1: enable 1 r/w enable blue input port (for manual use, cut off 50ohm internal resistor) 0: disable (default) 1: enable 0 r/w crc check 0: stop 1: start crc check during the next full frame and clear after finish (crc value in reg. 0xc0) address: c3 analog_common_ctrl0 default: 03h bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 126 7:4 r resl<3:0> z0 value 0000: max. 1111: min. read back z0 value when calibration is finished. 3:0 r/w spadl<3:0>: selection tstpad mode for analog test 0000: 40u 0001: select tmds test signal (please reference crc 4 5 ) 0010: d2pl(for pwm0/tcon2) (pin 5) x011: p2dl (pad to digital, digital input 3.3v) (default) power on latch x1xx: hz 1000: a2p33v 1001: d2p33v in open drain mode 1010: d2p33v in ttl mode address: c4 analog_common_ctrl1 default: 00h bit mode function 7:6 r/w tmds_test normal output selection 00: pwm0 01: tcon2 10: irq# 11: rsv 5 r/w entstl : enable internal test signal list below 0: off 1: on 4:0 r/w spadtstl<4:0>: select test signal (spadl<3:0>=0001b) 00x00 clkpllpowl 10010 fin in green port 00x01 lprst in clk port 10011 fbak in green port 00x10 fin in clk port 10100 ck2.5x sampling clk in green port 00x11 fbak in clk port 10101 ck2.5x in green port 01000 blupowl 10110 ck1.0x in green port 01001 lprst in blue port 10111 ck0.5x in green port 01010 fin in blue port 11000 redpowl 01011 fbak in blue port 11001 lprst in red port 01100 ck2.5x sampling clk in blue 11010 fin in red port 01101 ck2.5x in blue port 11011 fbak in red port 01110 ck1.0x in blue port 11100 ck2.5x sampling clk in red port 01111 ck0.5x in blue port 11101 ck2.5x in red port 10000 grnpowl 11110 ck1.0x in red port http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 127 10001 lprst in green port 11111 ck0.5x in red port address: c5 analog_bias_ctrl default: 31h bit mode function 7 r/w auto equalizer setting by hw 0: disable 1: enable 7 r/w set 0 6:3 r/w sbiasl<3:0> (default: 0110) 2:0 r/w sbiasgenl<2:0> : bias generator (default: 001) address: c6 analog_common_ctrl2 default: 2xh bit mode function 7 r/w sibinl : select bias source 0: auto generate (default) 1: bias source is set to ib2in. 6:5 r/w paginl<1:0> : preamp gain selection of r/g/b port (default=01) 00: max. 11: min. 4 r/w analog equalizer enable(eneql) 0: disable (default) 1: enable 3 r tmds internal ctl3 signal status 2 r tmds internal ctl2 signal status 1 r tmds internal ctl1 signal status 0 r tmds internal ctl0 signal status address: c7 z0_calibration_ctrl2 default: a3h bit mode function 7 r/w stunel : select calibration 0: z0 is set by adjrl<3:0> (manual) 1: z0 is auto calibrated (default) 6 r/w z0powl : (control of clock channel internal 50ohm resistor) 50 ohm impedance match calibration starts after power is stable, then status changes from 0 1 0: off 1: on 5:2 r/w adjrl<3:0> : select z0 impedance value (default 1000) 1:0 r/w srextl<1:0> : select rext value (select corresponding rext value on the pcb to srextl) 00:4k 01:2k http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 128 10:4k/3 11:1k address: c8 clock_pll_setting default: 32h bit mode function 7 --- reserved to 0 6:5 r/w scklvcsetl<1:0 >: when reset clk pll, the reset value of vc node 00: 2.17v 01: 1.98v (default) 10: 1.79v 11: 1.60v 4:2 r/w sckil<2:0> : pll charge-pump current (default= 3 b100) 10u + <4>*20u + <3>*10u + <2>*10u 1:0 r/w sckrl<1:0> : pll lpf resistor 8k + <1>*4k + <0>*2k address: c9 rgb_pll_setting default: 28h bit mode function 7 --- reserved to 0 6:5 r/w ssavcsetl<1:0> : when reset r/g/b pll, the reset value of vc node 00: 2.17 01: 1.98 (default) 10: 1.79 11: 1.60 4:2 r/w ssail<2:0> : pll charge-pump current (default:3 b010) 10u+<4>*20u+<3>*10u+<2>*10u 1:0 r/w ssarl<1:0 >: pll lpf resistor (default: 2 b00) 8k+<1>*4k+<0>*2k address: ca watch_dog_ctrl default: 40h bit mode function 7 --- reserved to 0 6 r/w fifo r/w auto calibration 0: manual 1: auto (default) 5 r/w r channel manual mode 0: not invert (default) 1: invert 4 r/w g channel manual mode 0: not invert (default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 129 1: invert 3:2 r/w ckwdconl<1:0> : pll watch dog mode, when ckl<0.7mhz, reset pll (clock) 00: enable (default) 01: keep pll vco=sckvcsetl<1:0> (break pll loop) 1x: disable watch dog 1:0 r/w sawdconl<1:0> : pll watch dog mode, when ckl<0.7mhz, reset pll (sampling data) 00: enable (default) 01: keep pll vco=ssavcsetl<1:0> (break pll loop) 1x: disable watch dog address: cb cdr_ctrl0 default: 00x0_0010b bit mode function 7:6 r/w udcnt_sel<1:0> indicate which channel to be r/w in crcc[5], crcf (only when manual mode (crcf[7]=0)) 1x:red 01:green 00:blue 5 r ov_flag: when udcnt fall in undefined phase number (#80~127) 4 r/w ov_flag_cln: to clean ov_flag 3:2 r/w adj_gain<1:0> phase adjust gain. one up/down could mean to change the phase by 1~4 minimum step sizes. 1:0 r/w lpf<1:0> lpf selection 00: accumulation type x1: consecutive type, 10: cascade type. (consecutive accumulation) (default) address: cc cdr_ctrl1 default: 0ah bit mode function 7:0 thr_acc<7:0>: threshold to assert up/down in accumulation lpf address: cd cdr_ctrl2 default: 0ah bit mode function 7:0 r/w thr_consec<7:0>: threshold to assert up/down in consecutive lpf crcc and crcd values can t be zero. address: ce up_down_adjusting0 default: 80h bit mode function 7 r/w ud_auto : 1: auto; 0:manual 6:0 r/w udcnt_fw<6:0> specify which phase number (#0~79) sent to analog. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 130 address: cf up_down_adjusting1 default: 14h bit mode function 7:0 r/w wait_time<7:0>: the minimum period between two phases adjusts. (phase change responding time) address: d0 adaptive equalizer default: 00h bit mode function 7 r/w adaptive equalizer enable 0: disable 1: enable 6:5 r adaptive equalizer up/down by hw (cleared by writing crc6) 00: the same 01: down 1x: up 4:2 r/w accumulative times 000: 8 001: 16 111: 64 1:0 r/w hdcp mp test address: d1 up_down_ctrl0 default: 92h bit mode function 7 r/w adj_auto_r : phase adjusting automatically by digital or not, for red channel. 1: automatic (default) 0: manual by firmware 6:5 r/w updown_r<1:0>: manually adjust of up/down for pll, i n red channel. this is only useful when adj_auto_r is set to 0. 10: up 01: down 00: hold (default) 4 r/w adj_auto_g : phase adjusting automatically by digital or not, for green channel. 1: automatic (default) 0: manual by firmware 3:2 r/w updown_g<1:0>: manually adjust of up/down for pll, in green channel. this is only useful when adj_auto_r is set to 0. 10: up 01: down http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 131 00: hold (default) 1 r/w adj_auto_b :phase adjusting automatically by digital or not, for blue channel. 1: automatic (default) 0: manual by firmware 0 r/w up side down 0: disable 1: enable address: d2 up_down_ctrl1 default: 00 0 1_xxxxb bit mode function 7:6 r/w updown_b<1:0>: manually adjust of up/down for pll, in blue channel. this is only useful when adj_auto_r is set to 0. 10: up 01: down 00: hold 5 r/w reserved to 0 4 r/w nl_auto : frequency range selection by digital part automatically. 1: automatic by digital (default) 0: manual selected by firmware 3:0 r nl<3:0>: frequency selected by digital part. 0000: 0hz 0001: >165mhz or <25mhz 1110: 25-50 mhz 1000: 50-80 mhz 0110: 80-112 mhz 0100: 112-140 mhz 0011: 140-165 mhz otherwise: invalid address: d3 up_down_ctrl2 default: 30h bit mode function 7 r/w cptest 0: normal mode, in which clock and data from analog are used. 1: select tstckin/tstdin as input 2x5 clock and data respectively, for testing. 6:4 r/w stable_cnt<2:0>: numbers of consecutive frequency change command after which n_freq can be adjusted. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 132 3:0 r/w nl_fw<3:0>: frequency selected by firmware. t he valid values are the same as those listed in previous row. (read back value in crd3) address: d4 up_down_crtl3 default: 00h bit mode function 7:6 r/w errc_sel<1:0> 00: original signal 01: debouncing 1 cycle 10: debouncing 1+8 cycle 11: 1+8 cycle debouncing+ de masking transition of vs/hs+vs+(hs88) to masking de 5:0 r/w debug_sel hdcp address: d5 hdcp ctrl default : 0000_0000b bit mode function 7 r/w hdcp key access sram bist action 0: stop & clear after finish. 1: start 6 r hdcp key access sram bist status 0: fail 1: ok, when test start, clear this bit 5 r indicate vsync polarity 0: positive, which means vs pulse is high. 1: negative 4 r/w invert vsync for hdcp 0: not inverted 1: inverted 3 r/w indicate vsync polarity mode: 0: auto, indicate by 0x70[5] 1: manual, decided by 0x70[4] 2 r/w mcu access ddc data first 0: enable ddc channel and mcu access only when ddc is not busy 1: disable ddc channel and mcu access only 1 r/w device key access port download enable 0: disable, this would reset the address of device key access port to 0. 1: enable 0 r/w hdcp enable 0: disable hdcp, except for output. 1: auto enable hdcp function, when tx i2c write aksv http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 133 address: d6 device key access port bit mode function 7:0 r/w when enable device key accessing 40x56 table, the 56-bit key table will be transferred to 64-bit pseudo data with 7 th , 15 th , 23rd, 31st, 39 th , 47 th , 55 th bits inserted. the inserted data are 0 .and the write sequence is: {d0-byte0, d0-byte1, d0-byte2, d0-byte3,d0-byte4, d0-byte5, d0-byte6, d0-byte7}, {d1-byte0, d1-byte1, 1-byte2,d1-byte3, d1-byte4, d1-byte5, d1-byte6, d1-byte7}, accessing this port must be coded/decoded by realtek protection code. address: d7 hdcp_port_ctrl default: 00h bit mode function 7:1 -- reserved 0 r/w hdcp accessing port auto increase (for host side) 0: auto increase 1: keep in the same address. address: d8 hdcp_addr_port default: 00h bit mode function 7:0 r/w address port for embedded hdcp access, auto increase after data_port being accessed . (for host side controlled by d7) address: d9 hdcp_data_port bit mode function 7:0 r/w data port for embedded hdcp access i2c control register map ( mcu side ) hex address write / read size in bytes default value register name function 0x00 r/w 5 xx_xx_xxbksv hdcp receiver ksv. this value may be used to determine that the http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 134 _xx_xx receiver is hdcp capable. valid ksvs contain 20 ones and 20 zeros, a characteristic that must be veri fied by hdcp transmitters before encryption is enabled. this value must be available any time the hdcp receiver s hdcp hardware is ready to operate. 0x05 r 3 all 0, no reg reserved all bytes read as 0x00 0x08 r 2 xx_xx ri link verification response. up on completion of the authentication computations, this register contains the r0' value. following that, it is updated upon completion of hdcpblockcipher if (i mod 128) == 0. it is recommended that hdcp transmitters protect against errors in the i2c transmission by re- reading this value when unexpected values are received, though care must be taken to avoid missing legitimate mis - match conditions. this value must be available at all times between updates. r0' must be available less than 100 ms after a ksv is received. subsequent ri' values must be available a maximum of 128 pixel clocks following the encryption enable detection (enc_en). 0x0a r 1 xx pj enhanced link verification response. updated upon receipt of first video pixel received when frame counter value (j mod 16) == 0. the value is the xor of the decrypted byte on channel zero of the first video pixel with the least significant byte of rj. rj is derived from the output function in the same manner as ri, but is captured every 16 th counted frame (rather than every 128 th counted frame). 0x0b r 5 all 0, no reg reserved all bytes read as 0x00 0x10 r 5 xx_xx_xx _xx_xx aksv hdcp transmitter ksv. writes to this multi-byte value are written least significant byte first. the final write to 0x14 triggers the authentication sequence in the hdcp receiver, and the current ainfo value is copied from the port, takes effect, and the port is reset to the default value of zero. 0x15 r 1 00 ainfo bits 7-2: reserved zeros. bit 1: enable_1.1_features. this bit enables the advance cipher option. if in dvi mode, it also enables the enhanced encryption status signaling (eess). this bit resets to default zero when the hdcp receiver becomes attached or active, or is reset, or the last byte of aksv is written. a write to the last byte of aksv copies the port value and causes it to take effect, and then resets the port value to the default value of zero. thus the options must be explicitly enabled prior to each authentication. bit 0: reserved (must be zero). http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 135 0x16 r 2 00_00 no reg reserved all bytes read as 0x00 0x18 r 8 an session random number. this multi-byte value must be written by the hdcp transmitter before the ksv is written. 0x20 r 20 0, no reg reserved all bytes read as 0x00 0x34 r 12 0, no reg reserved all bytes read as 0x00 0x40 [7] r/w [6:5] r, [4] r ( or needs option for system ?) [3:2] r [1] r/w [0] r 1 8 b10010011 bcaps bit 7: hdmi_reserved use of this bit is reserved. bit 6: repeater, hdcp repeater capability. when set to one, this hdcp receiver supports downstream connections as permitted by the digital content protection llc license. this bit does not change while the hdcp receiver is active. bit 5: ready, ksv fifo ready. when set to one, this hdcp repeater has built the list of attached ksvs and computed the verification value v . this value is always zero during the computation of v . bit 4: fast. when set to one, this device supports 400 khz transfers. when zero, 100 khz is the maximu m transfer rate supported. note that 400khz transfers are not permitted to any device unless all devices on the i 2 c bus are capable of 400khz transfer. the transmitter may not be able to determine if the edid rom, present on the hdcp receiver, is capable of 400khz operation. this bit does not change while the hdcp receiver is active. bits 3-2: reserved (must be zero). bit 1: 1.1_features. when set to one, this hdcp receiver supports enhanced encryption status signaling (eess), advance cipher, and enhanced link verification options. this bit does not change while the hdcp receiver is active. bit 0: fast_reauthentication. when set to 1, the receiver is capable of receiving (unencrypted) video signal during the session re-authentication. this bit does not change while the hdcp receiver is active. 0x41 r 2 00 bstatus refer to table 1 0x43 r 1 00 ksv fifo key selection vector fifo. this device is not a repeater. all byte read as 0x00 for hdcp receivers that are not hdcp repeaters(repeater==0). 0x44 r 124 0, no reg reserved all bytes read as 0x00 the useful bytes of this ddc port are too few. we could use latch file to replace sram. when read non-defined address, output 0. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 136 name bit field default value read /write description reserved 15:14 00 r read as zero. hdmi_reserved_2 13 0 r/w reserved for future possible hdmi use. hdmi_mode 12 0 r/w hdmi mode. when set to one, the hdcp receiver has transitioned from dvi mode to hdmi mode. this has occurred because the hdcp receiver has detected hdmi bus conditions on the link. this bit must not be cleared when the hdcp transmitter and hdcp receiver are connected and both are operating in an active hdmi mode. this bit must be cleared upon power- up, reset, unplug or plug of an hdcp transmitter or anytime that the hdcp receiver has not seen at least one data island within 30 video frames. for clear conditions circuit could tell, such as no di within 30 video frames, reset, and power-up reset, circuit should clear this bit. in other conditions such as unplug or plug, we could use f/w write 0 to clear this bit. 11:0 0, no reg r read as zero. table 1 (address 0x41) i2c control register map (dvi ddc side) device address : 0x74/0x75 hex address write/ read size in bytes register name function 0x00 r 5 bksv hdcp receiver ksv. this value may be used to determine that the rec eiver is hdcp capable. valid ksvs contain 20 ones and 20 zeros, a characteristic that must be verified by hdcp transmitters before encryption is enabled. this value must be available any time the hdcp receiver s hdcp hardware is ready to operate. 0x05 r 3 reserved all bytes read as 0x00 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 137 0x08 r 2 ri link verification response. upon completion of the authentication computations, this register contains the r0' value. following that, it is updated upon completion of hdcpblockcipher if (i mod 128) == 0. it i s recommended that hdcp transmitters protect against errors in the i2c transmission by re- reading this value when unexpected values are received, though care must be taken to avoid missing legitimate mis -match conditions. this value must be available at a ll times between updates. r0' must be available less than 100 ms after a ksv is received. subsequent ri' values must be available a maximum of 128 pixel clocks following the encryption enable detection (enc_en). 0x0a r 1 pj enhanced link verification response. updated upon receipt of first video pixel received when frame counter value (j mod 16) == 0. the value is the xor of the decrypted byte on channel zero of the first video pixel with the least significant byte of rj. rj is derived from the output func tion in the same manner as ri, but is captured every 16 th counted frame (rather than every 128 th counted frame). 0x0b r 5 reserved all bytes read as 0x00 0x10 r/w 5 aksv hdcp transmitter ksv. writes to this multi-byte value are written least significant byte first. the final write to 0x14 triggers the authentication sequence in the hdcp receiver, and the current ainfo value is copied from the port, takes effect, and the port is reset to the default value of zero. 0x15 r/w 1 ainfo bits 7-2: reserved zeros. bit 1: enable_1.1_features. this bit enables the advance cipher option. if in dvi mode, it also enables the enhanced encryption status signaling (eess). this bit resets to default zero when the hdcp receiver becomes attached or active, or is reset, or the last byte of aksv is written. a write to the last byte of aksv copies the port value and causes it to take effect, and then resets the port value to the default value of zero. thus the options must be explicitly enabled prior to each authentication. bit 0: reserved (must be zero). 0x16 r 2 reserved all bytes read as 0x00 0x18 r/w 8 an session random number. this multi-byte value must be written by the hdcp transmitter before the ksv is written. 0x20 r 20 reserved all bytes read as 0x00 0x34 r 12 reserved all bytes read as 0x00 0x40 r 1 bcaps bit 7: hdmi_reserved use of this bit is reserved. bit 6: repeater, hdcp repeater capability. when set to one, this hdcp receiver supports downstream connections as permitted by the digital content http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 138 protection llc license. this bit does not change while the hdcp receiver is active. bit 5: ready, ksv fifo ready. when set to one, this hdcp repeater has built the list of attached ksvs and computed the verification value v . this value is always zero during the computation of v . bit 4: fast. when set to one, this device supports 400 khz transfers. when zero, 100 khz is the maximu m transfer rate supported. note that 400khz transfers are not permitted to any device unless all devices on the i 2 c bus are capable of 400khz transfer. the transmitter may not be able to determine if the edid rom, present on the hdcp receiver, is capable of 400khz operation. this bit does not change while the hdcp receiver is active. bits 3-2: reserved (must be zero). bit 1: 1.1_features. wh en set to one, this hdcp receiver supports enhanced encryption status signaling (eess), advance cipher, and enhanced link verification options. this bit does not change while the hdcp receiver is active. bit 0: fast_reauthentication. when set to 1, the receiver is capable of receiving (unencrypted) video signal during the session re- authentication. this bit does not change while the hdcp receiver is active. 0x41 r 2 bstatus refer to table 1 0x43 r 1 ksv fifo key selection vector fifo. this device is not a repeater. all byte read as 0x00 for hdcp receivers that are not hdcp repeaters(repeater==0). 0x44 r 124 reserved all bytes read as 0x00 name bit field read/ write description reserved 15:14 r read as zero. hdmi_reserved_2 13 r reserved for future possible hdmi use. hdmi_mode 12 r hdmi mode. when set to one, the hdcp receiver has transitioned from dvi mode to hdmi mode. this has occurred because the hdcp receiver has detected hdmi bus conditions on the link. this bit must not be cleared when the hdcp transmitter and hdcp receiver are connected and both are operating in an active hdmi mode. this bit must be cleared upon power- up, reset, unplug or plug of an hdcp transmitter or anytime that the hdcp receiver has not seen at least one data island within 30 video http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 139 frames. 11:0 r read as zero. table 1 (address 0x41) note : 1. when accessing this ddc register map by ddc, the address should increase automatically, except for the first accessing address is ksv_fifo, 0x43. 2. access has an implicit offset address equal to 0x08. address: d9-c0 hdcp frame counter default: 0 bit mode function 7 r read as 0 6:0 r hdcp_frame counter [6:0] address: d9-c1 bit mode function 7:0 r reserved address: d9-c2 hdcp system. info default: 00000000b bit mode function 7 --- reserved 6 r authst (means bksv of rtd pass tx authorization, tx is ready to do hdcp transaction) 5 r authkm (means rtd finish computing km, ri) //hidden 4 r authdone (means tx admitted ri value, start to do hdcp transmission) 3:2 -- reserved 1 r no ctrl3, hdcp 1.0 fail flag 0 r internal buffer for ainfo[1]. since ainfo[1] in ddc port is 0 at most of time, we need to know what tx wrote. address: d9-c3 hdcp flow control default: 0000_0000b bit mode function 7:4 r/w reserved to 0 3 r/w enc_en / enc_dis error correction for eess mode http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 140 0: enc_en: ctl3~ctl0=1001; enc_dis: ctl3~ctl0=0001 1: enc_dis = ~ enc_en 2 r enc_en status 1 r enc_dis status 0 r enc_en | enc_dis watch dog address: da watch_dog_ctrl default: 00h bit mode function 7:6 -- reserved to 0 5 r/w auto switch when display vsync timeout 0: disable (default) 1: enable 4 r/w auto switch when adc-pll non-lock 0: disable (default) 1: enable 3 r/w auto switch when overflow or underflow 0: disable (default) 1: enable 2 r/w auto switch event happen action (for timing) 0: disable (default) 1: free run 1 r/w auto switch event happen action (for data) 0: disable (default) 1: background turn off overlay enable and switch to background simultaneously. 0 r display vsync timeout flag (status with crda [5]) 0: vsync is present 1: vsync timeout the line number of display hs is equal to display vertical total; this bit is set to 1 . write to clear status. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 141 embedded adc address: dc adc access port default: 00h bit mode function 7 r/w enable adc access port 6:5 r/w reserved to 0 4:0 r/w adc port address address: dd adc data port bit mode function 7:0 r/w adc data port address: dd-00 adc_ rgb_ctrl default: 56h bit mode function 7:6 r/w pga (00: ash=0.9 01: ash=1.0 10: ash=1.1 11: ash=1.2) (default: 01) 5:4 r/w pga (00: aref=0.9 01: aref=1.0 10: aref=1.1 11: aref=1.2)(default: 01) 3 r/w adc source select (need to select corresponding adc_out_sog 0 or 1) 0 : input0 (default) 1 : input1 2 r/w adc input mode selection 0 : single ended 1 : differential (default) 1:0 r/w bandwidth adjustment 00 : 75m 01 : 150m 10 : 300m (default) 11 : 500m address: dd-01 adc_ red_ctrl default: 40h bit mode function 7 r/w red channel clamp mode selection 0: low clamp (default) 1: middle clamp 6:4 r/w red channel clamp voltage 0~700mv, step=100mv (default: 100) 3 r/w red channel offset depends on gain 0: rgb dependent, ypbpr independent (default) 1: rgb independent, ypbpr independent 2:0 r/w red channel adc fine tune delay (step=90ps) (default: 000) address: dd-02 adc_grn_ctrl default: 40h bit mode function 7 r/w green channel clamp mode selection 0: low clamp (default) 1: middle clamp 6:4 r/w green channel clamp voltage 0~700mv, step=100mv(default:100) 3 r/w green channel offset depends on gain 0: rgb dependent, ypbpr independent(default) 1: rgb independent, ypbpr independent 2:0 r/w green channel adc fine tune delay (step=90ps) (default:000) address: dd-03 adc_blu_ctrl default: 40h bit mode function 7 r/w blue channel clamp mode selection 0: low clamp(default) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 142 1: middle clamp 6:4 r/w blue channel clamp voltage 0~700mv, step=100mv (default:100) 3 r/w blue channel offset depends on gain 0: rgb dependent, ypbpr independent(default) 1: rgb independent, ypbpr independent 2:0 r/w blue channel adc fine tune delay (step=90ps) (default: 000) address: dd-04 red_gain default: 80h bit mode function 7:0 r/w red channel gain adjust address: dd-05 grn_gain default: 80h bit mode function 7:0 r/w green channel gain adjust address: dd-06 blu_gain default: 80h bit mode function 7:0 r/w blue channel gain adjust address: dd-07 red_offset default: 80h bit mode function 7:0 r/w red channel offset adjust address: dd-08 grn_offset default: 80h bit mode function 7:0 r/w green channel offset adjust address: dd-09 blu_offset default: 80h bit mode function 7:0 r/w blue channel offset adjust address: dd-0a sog0_ctrl default: 20h bit mode function 7 r/w r channel clamp to top 0: normal (0.375v) 1: top (0.75v) 6 r/w g channel clamp to top 0: normal (0.375v) 1: top (0.75v) 5:0 r/w sog0 reference control 0~630mv, step=10mv (default: 100000) address: dd-0b sog1_ctrl default: 20h bit mode function 7 r/w b channel clamp to top 0: normal (0.375v) 1: top (0.75v) 6 r/w r, b clamp value from g 0: no 1: yes 5:0 r/w sog1 reference control 0~630mv, step=10mv (default: 100000) l the lowest voltage of sog_in is clamped to about 200mv. l sog reference control set the threshold voltage to extract the sync signal from g. the threshold voltage maps the value 0~63 to 0~630 mv. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 143 sog_insog_shift level_shift sog_compare (minimum voltage at 200mv) (compare 0~630mv, step 10mv) capacitor 0v -300mv 0v 200mv 500mv compare voltage(0~630mv) address: dd-0c adc_power_ctrl default: 08h bit mode function 7 r/w sog mode 0: nmos/r 1: clamping 6 r/w sog channel clamp to C 300mv 0: 500mv 1: 200mv 5 r/w sog0 power on 0 : power down(default) 1 : power on 4 r/w sog1 power on 0 : power down(default) 1 : power on 3 r/w band-gap power on 0 : power down 1 : power on (default) 2 r/w red channel adc power on 0 : power down (default) 1 : power on 1 r/w green channel adc power on 0 : power down (default) 1 : power on 0 r/w blue channel adc power on 0 : power down (default) 1 : power on l note that band-gap power can only turn off just in the power down mode, or the chip may run abnormally. l when in power saving mode, only r/g/b channel will be power down, it doesn t include the sog & band-gap. address: dd-0d adc_clock default: 01h bit mode function 7 r/w input clock polarity 0: negative (default) 1: positive 6 r/w output clock polarity 0: normal (default) 1: inverted 5:4 r/w adc_out pixel extra delay 00: 1.05ns (default) 01: 1.39ns 10: 1.69ns 11: 1.97ns http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 144 3 r/w 1x or 2x from apll (for better clock duty cycle) 0: 1x (default) 1: 2x 2 r/w single ended or differential clock from apll 0: differential (default) 1: single ended 1:0 r/w duty stablizer (default: 01) address: dd-0e adc_test default: 04h bit mode function 7 r/w reserved to 0 6:4 r/w test output selection (pad : sogin0/sogin1) 000:x/x(hi-z) normal sog mode (default) 001:gnd/gnd 010:vrbir/vrefn 011:vcmi/vcmo 100:vrtir/vrefp 101:vmid/gnd 110:voffset/gnd 111:vdd/vdd 3:2 r/w sog resistor 00: open 01: poly r=500k, external c=10nf (default) 10: mos r=1m, external c=4.7nf 11: mos r=5m, external c=1nf 1:0 r/w clock output divider 00 : 1/1 (default) 01 : 1/2 10 : 1/3 11 : 1/4 address: dd-0f adc_ibias2 default: 53h bit mode function 7:6 r/w apll_ib60u[1:0] bias current of apll_ib60u 00:48u 01:60u (default) 10:72u 11:84u 5:4 r/w adc_sf[1:0] bias current of adc_sf 00:15u 01:20u (default) 10:25u 11:30u 3 r/w adc_ref bias current of adc_ref 0:60u (default) 1:80u http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 145 2:0 r/w adc_op[2:0] bias current of adc_op 000:10u 001:15u 010:17.5u 011:20u 100:22.5u 101:25u 110:27.5u 111:30u address: dd-10 adc_vbias0 default: 21h bit mode function 7 r/w resistor reference (refio) 0:ref. to internal r (default) 1:ref. to external r=2k 6:4 r/w adc_vbias0[6:4] band gap voltage 000:0.890 001:0.841 010:0.792 (default) 011:0.742 100:0.693 101:0.644 110:0.594 111:0.545 3:2 r temperature sensor 0~120 (70+38*1.2) 00: 30 degree 01: 30-60 degree 10: 60-90 degree 11: 120 degree 1:0 r/w adc_vbias0[1:0] band gap voltage 00:0.775 01:0.792 (default) 10:0.810 11:0.829 address: dd-11 adc_vbias1 default: 0dh bit mode function 7 r/w adc gain calibration 0: normal 1: calibration 6 r/w r channel clamp to -300mv 0: 0mv (default) 1: -300mv 5 r/w g channel clamp to -300mv 0: 0mv (default) 1: -300mv 4 r/w b channel clamp to -300mv 0: 0mv (default) 1: -300mv 3 r/w vcmo with lower vdd ratio //(1) 0:lower,1.068 1:normal, 1.122 (default) 2 r/w vcmo from vbg or from vdd //(1) 0:from vbg (constant) 1:from vdd (default) 1:0 r/w vcmo voltage[1:0] //(01) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 146 00:0.90 01:1.00 (default) 11:1.05 11:1.10 address: dd-12 ptnpos_h default: 00h bit mode function 7 r/w enable test 0: finish (and result sequence is r-g-b) (default) 1: start 6:4 r/w test pattern v position register [10:8] assign the test pattern digitized position in line after v_start. 3 -- reserved to 0 2:0 r/w test pattern h position register [10:8] assign the test pattern digitized position in pixel after h_start. address: dd-13 ptnpos_v_l bit mode function 7:0 r/w test pattern v position register [7:0] assign the test pattern digitized position in line after v_start.. address: dd-14 ptnpos_h_l bit mode function 7:0 r/w test pattern h position register [7:0] assign the test pattern digitized position in line after h_start.. use ptnpos to assign the pixel position after hsync leading edge that input signal digitized. each time the ptnpos is written, the digitized results will be loaded into ptnrd, ptngd and ptnbd. for test issue, make the input signal a fixed pattern before ptnpos is written. then the same digitized output will be got. address: dd-15 ptnrd bit mode function 7:0 r test pattern red-channel digitized result. address: dd-16 ptnrd bit mode function 7:0 r test pattern green-channel digitized result. address: dd-17 ptnrd bit mode function 7:0 r test pattern blue-channel digitized result. l the test pattern digitized result after hsync leading edge about ptnpos pixel. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 147 icm address: e0 icm control default: 00h bit mode function 7 r/w icm enable 0: disable 1: enable 6 r/w y correction 0: disable 1: enable 5 r/w reserved to 0 4 r/w cm0 enable 0: disable 1: enable 3 r/w cm1 enable 0: disable 1: enable 2 r/w cm2 enable 0: disable 1: enable 1 r/w cm3 enable 0: disable 1: enable 0 r/w cm4 enable 0: disable 1: enable address:e1 icm_sel default: 00h bit mode function 7:5 r/w icm test mode 000: disable 001: bypass u, v result 010: bypass hue/saturation result 011: bypass du, dv value 1xx: r,b as lut input, and bypass lut output to r/g/b output 4:3 -- reserved 2:0 r/w cm select 000: select chroma modifier 0 for accessing through data port 001: select chroma modifier 1 for accessing through data port 010: select chroma modifier 2 for accessing through data port 011: select chroma modifier 3 for accessing through data port 100: select chroma modifier 4 for accessing through data port 101~111: reserved address:e2 icm_addr default: 00h bit mode function 7:0 r/w icm port address address:e3 icm _data bit mode function 7:0 r/w icm port data icm_addr will be increased automatically after each byte of icm_data has been accessed. address: e3-00 mst_hue_hb default: x0h bit mode function 7:4 -- reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 148 3:0 w high byte[11:8] of master hue for chroma modifier n. address: e3-01 mst_hue_lb default: 00h bit mode function 7:0 w low byte[7:0] of master hue for chroma modifier n. address: e3-02 hue_set default: 00h bit mode function 7:6 w cm[n]_lwid 00: cm[n] left width 0 01: cm[n] left width 1 10: cm[n] left width 2 11: cm[n] left width 3 5:4 w cm[n]_lbuf 00: cm[n] left buffer 0 01: cm[n] left buffer 1 10: cm[n] left buffer 2 11: cm[n] left buffer 3 3:2 w cm[n]_rwid 00: cm[n] right width 0 01: cm[n] right width 1 10: cm[n] right width 2 11: cm[n] right width 3 1:0 w cm[n]_rbuf 00: cm[n] right buffer 0 01: cm[n] right buffer 1 10: cm[n] right buffer 2 11: cm[n] right buffer 3 address: e3-03~32 u/v offset default: 00h bit mode function 7:0 w addr 03: u offset 00, addr 04: v offset 00, addr 05: u offset 01, addr 06: v offset 01, addr 07: u offset 02, addr 08: v offset 02, addr 09: u offset 03, addr 0a: v offset 03, addr 0b: u offset 04, addr 0c: v offset 04, addr 0d: u offset 05, addr 0e: v offset 05, addr 0f: u offset 06, addr 10: v offset 06, addr 11: u offset 07, addr 12: v offset 07, addr 13: u offset 10, addr 14: v offset 10, addr 15: u offset 11, addr 16: v offset 11, addr 17: u offset 12, addr 18: v offset 12, addr 19: u offset 13, addr 1a: v offset 13, addr 1b: u offset 14, addr 1c: v offset 14, http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 149 addr 1d: u offset 15, addr 1e: v offset 15, addr 1f: u offset 16, addr 20: v offset 16, addr 21: u offset 17, addr 22: v offset 17, addr 23: u offset 20, addr 24: v offset 20, addr 25: u offset 21, addr 26: v offset 21, addr 27: u offset 22, addr 28: v offset 22, addr 29: u offset 23, addr 2a: v offset 23, addr 2b: u offset 24, addr 2c: v offset 24, addr 2d: u offset 25, addr 2e: v offset 25, addr 2f: u offset 26, addr 30: v offset 26, addr 31: u offset 27, addr 32: v offset 27, dcc address: e4 dcc_ctrl0 default: 00h bit mode function 7 r/w dcc_enable 0: disable 1: enable 6 r/w y_formula 0: formula 0 1: formula 1 5 r/w soft_clamp 0: disable 1: enable 4 r/w dcc_mode 0: auto mode offset 07 offset 17 offset 10 offset 27 offset 20 offset 00 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 150 1: manual mode 3 r/w scene_change 0: disable scene-change function 1: enable scene-change function in auto mode 2 r/w bwl_exp 0: disable black/white level expansion 1: enable black/white level expansion in auto mode 1:0 r/w dcc_page_sel 00: page 0 (for histogram / ymin-max / soft-clamping / scene-change) 01: page 1 (for y-curve / wbl expansion) 10: page 2 (for calculation parameter) 11: page 3 (for testing and debug) address: e5 dcc_ctrl1 default: 00h bit mode function 7 r/w dcc gain control enable 0: disable 1: enable note: dcc gain control enable must delay mov_avg_len frame after dcc enable. 6 r 1: time to write highlight window position & normalized factor, write to clear 5:0 -- reserved 0 address: e6 dcc address port bit mode function 7:0 r/w dcc address address: e7 dcc data port bit mode function 7:0 r/w dcc data dcc_addr will be increased automatically after each byte of dcc_data has been accessed. address: e7-00 (page0) nor_factor_h bit mode function 7:6 -- reserved 5:0 r/w bit[21:16] of normalized factor; nf=(255/n)*(2^22) address: e7-01 (page0) nor_factor_m bit mode function 7:0 r/w bit[15:8] of normalized factor; nf=(255/n)*(2^22) address: e7-02 (page0) nor_factor_l bit mode function 7:0 r/w bit[7:0] of normalized factor; nf=(255/n)*(2^22) address: e7-03 (page0) bbe_ctrl default: 04h bit mode function 7 r/w bbe_ena 0: disable black-background exception 1: enable black-background exception 6:4 -- reserved 3:0 r/w bbe_thd http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 151 8-bit rgb threshold for black-background exception address: e7-04 (page0) nflt_ctrl default: 00h bit mode function 7 r/w hnflt_ena 0: disable histogram noise filter 1: enable histogram noise filter 6:4 r/w hnflt_thd threshold for histogram noise filter 3 r/w ynflt_ena 0: disable ymax / ymin noise filter 1: enable ymax / ymin noise filter 2:0 r/w ynflt_thd threshold for ymax/ymin noise filter (= 4*ynflt_thd) address: e7-05 (page0) hist_ctrl default: 00h bit mode function 7 r/w rh0_limiter 0: disable rh0 limiter 1: enable rh0 limiter 6 r/w rh1_limiter 0: disable rh1 limiter 1: enable rh1 limiter 5:3 -- reserved 2:0 r/w mov_avg_len 000: histogram moving average length = 1 001: histogram moving average length = 2 010: histogram moving average length = 4 011: histogram moving average length = 8 100: histogram moving average length = 16 101~111: reserved address: e7-06 (page0) soft_clamp default: b0h bit mode function 7:0 r/w slope of soft-clamping (= soft_clamp / 256) address: e7-07 (page0) y_max_lb default: ffh bit mode function 7:0 r/w lower bound of y_max (= 4*y_max_lb) address: e7-08 (page0) y_min_hb default: 00h bit mode function 7:0 r/w higher bound of y_min (= 4*y_min_hb) address: e7-09 (page0) scg_period default: xxx10000b bit mode function 7:5 -- reserved 4:0 r/w scene-change mode period = 1~32. note: scg_period >= mov_avg_len, cre7-05[2:0](page0) address: e7-0a (page0) scg_lb default: 00h bit mode function 7:0 r/w scg_diff lower bound for exiting scene-change mode address: e7-0b (page0) scg_hb default: ffh http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 152 bit mode function 7:0 r/w scg_diff higher bound for exiting scene-change mode address: e7-0c (page0) popup_ctrl bit mode function 7:1 reserved 0 r reg[0d]~reg[16] are updated every frame. once popup_bit is read, the value of reg[0d] ~ reg[16] will not be updated until reg[16] is read. address: e7-0d (page0) scg_diff bit mode function 7:0 r = (histogram difference between current frame and average) / 8 address: e7-0e (page0) y_max_val bit mode function 7:0 r = max { y_max_lb, (y maximum in current frame / 4) } address: e7-0f (page0) y_min_val bit mode function 7:0 r = min { y_min_hb, (y minimum in current frame / 4) } address: e7-10 (page0) s0_value bit mode function 7:0 r normalized histogram s0 value address: e7-11 (page0) s1_value bit mode function 7:0 r normalized histogram s1 value address: e7-12 (page0) s2_value bit mode function 7:0 r normalized histogram s2 value address: e7-13 (page0) s3_value bit mode function 7:0 r normalized histogram s3 value address: e7-14 (page0) s4_value bit mode function 7:0 r normalized histogram s4 value address: e7-15 (page0) s5_value bit mode function 7:0 r normalized histogram s5 value address: e7-16 (page0) s6_value bit mode function 7:0 r normalized histogram s6 value address: e7-00 (page1) def_crv[01] default:10h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-01 (page1) def_crv[02] default:20h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-02 (page1) def_crv[03] default:30h bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 153 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-03 (page1) def_crv[04] default:40h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-04 (page1) def_crv[05] default:50h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-05 (page1) def_crv[06] default:60h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-06 (page1) def_crv[07] default:70h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-07 (page1) def_crv[08] default:80h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-08 (page1) def_crv[09] default:90h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-09 (page1) def_crv[10] default:a0h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-0a (page1) def_crv[11] default:b0h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-0b (page1) def_crv[12] default:c0h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-0c (page1) def_crv[13] default:d0h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-0d (page1) def_crv[14] default:e0h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] address: e7-0e (page1) def_crv[15] default:f0h bit mode function 7:0 r/w pre-defined y-curve; keep def_crv[n] def_crv[n-1] registers below is effective only when auto mode is disable and black/white level expansion is enabled. when auto mode is enabled (dcc_mode=0), y_bl_bias and y_wl_bias are read-only. address: e7-0f (page1) y_bl_bias default:00h bit mode function 7:0 r/w y offset for black-level expansion (y_l' = 4*y_bl_bias) address: e7-10 (page1) y_wl_bias default:00h bit mode function 7:0 r/w y offset for while-level expansion ( 1023-y_h' = 4*y_wl_bias) load double buffer cre7-00 ~ cre7-10 (page1) after write cre7-10 when dcc enable registers below is effective only when auto mode is enabled. in manual mode (dcc_mode=1), bld_val will be fixed to 0. it means y-curve is fully determined by http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 154 def_cur[01~15] address: e7-11 (page1) bld_ub default:00h bit mode function 7:0 r/w upper bound of blending factor address: e7-12 (page1) bld_lb default:00h bit mode function 7:0 r/w lower bound of blending factor address: e7-13 (page1) dev_factor default:00h bit mode function 7:0 r/w deviation weighting factor address: e7-14 (page1) bld_val bit mode function 7:0 r blending value address: e7-15 (page1) dev_val_hi bit mode function 7:0 r bit[8:1] of deviation value address: e7-16 (page1) dev_val_lo bit mode function 7 r bit[0] of deviation value 6:0 -- reserved address: e7-00~8f (page2) sram initial value bit mode function 7:0 w hidden address: e7-00 (page3) sram_bist default: 00h bit mode function 7 r/w bist_en 0: disable 1: enable 6 r/w ram_mode 0: dclk domain mode (normal mode, bist) 1: mcu domain mode (scg test) 5:2 -- reserved 1 r bist_period 0: bist is done 1: bist is running 0 r bist_ok 0: sram fail 1: sram ok cyclic-redundant-check address: f2 op_crc_ctrl (output crc control register) default: 00h bit mode function 7:1 -- reserved to 0 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 155 0 r/w output crc control: 0: stop or finish (auto-stop after checked a completed display frame) (default) 1: start crc function = x^24 + x^7 + x^2 + x + 1. address: f3 op _crc_checksum (output crc checksum) bit mode function 7:0 r/w 1 st read=> output crc-24 bit 23~16 2 nd read=> output crc-24 bit 15~8 3 rd read=> out put crc-24 bit 7~0 l the read pointer should be reset when 1. op_crc_byte is written 2. output crc control starts. l the read back crc value address should be auto-increase, the sequence is shown above http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 156 ddc special function access (ddc/ci) address: f4 ddc_set_slave default: 6e bit mode function 7:1 r/w ddc slave address to decode 0 -- reserved to 0 address: f5 ddc_sub_in bit mode function 7:0 r ddc sub-address received address: f6 ddc_data_in bit mode function 7:0 r/w read: ddc data received (16-bytes buffer) write: ddc data received (16-bytes buffer) every read/write access, the buffer index is auto-decreased/increased. address: f7 ddc_ctrl default: 00h bit mode function 7 r/w start bist function for ddc sram 0: finished and clear 1: start 6 r test result about dvi ddc sram 0: fail 1: ok 5 r test result about adc ddc sram 0: fail 1: ok 4 -- reserved 3 r/w auto reset ddc_data buffer 0: disable 1: enable in host (pc) write enable, when ddc write (no start after ddc_sub), reset ddc_data buffer. 2 r/w reset ddc_data buffer 0: finish 1: reset 1 r/w ddc_data buffer write enable 0: host (pc) write enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 157 1: slave (mcu) write enable both pc and mcu can read ddc_data buffer, but only one can write ddc_data buffer. 0 r/w channel select 0: from adc ddc 1: from dvi ddc address: f8 ddc_status bit mode function 7 r ddc_data_buffer full if ddc_data buffer is full, this bit is set to 1 . (on-line monitor) the ddc_data buffer full status will be on-line-monitor the condition, once it becomes full, it kept high, if it is not-full, then it goes low. 6 r ddc_data_buffer empty if ddc_data buffer is empty, this bit is set to 1 . (on-line monitor) the ddc_data buffer empty status will be on-line-monitor the condition, once it becomes empty, it kept high, if it is not-empty, then it goes low. 5 -- reserved to 0 4 r if ddc_stop signal occurs, this bit is set to 1 . write clear. 3 r if ddc_data_out loaded to serial-out-byte, this bit is set to 1 . write clear 2 r if ddc_data_in latched, this bit is set to 1 . write clear 1 r if ddc_sub latched, this bit is set to 1 write clear 0 r if ddc_slave latched, this bit is set to 1 write clear when ddc start, clear ddc_stop flag, crf8[4]. address: f9 ddc_irq_ctrl default: 00h bit mode function 7 r/w 0: disable the ddc_data_buffer full signal as an interrupt source 1: enable the ddc_data_buffer full signal as an interrupt source 6 r/w 0: disable the ddc_data_buffer empty signal as an interrupt source 1: enable the ddc_data_buffer empty signal as an interrupt source 5 --- reserved 4 r/w 0: disable the ddc_stop signal as an interrupt source 1: enable the ddc_stop signal as an interrupt source 3 r/w 0: disable the ddc_data_out loaded to serial-out-byte as an interrupt source 1: enable the ddc_data_out loaded to serial-out-byte as an interrupt source 2 r/w 0: disable the ddc_data_in latched as an interrupt source 1: enable the ddc_data_in latched as an interrupt source 1 r/w 0: disable the ddc_sub latched as an interrupt source http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 158 1: enable the ddc_sub latched as an interrupt source 0 r/w 0: disable the ddc_slave latched as an interrupt source 1: enable the ddc_slave latched as an interrupt source http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 159 ddc channel (adc/dvi) (refers to the vesa display data channel standard for detailed) address: fa ddc_enable (ddc channel enable register) default: 00h bit mode function 7:5 r/w ddc channel address least significant 3 bits (the default ddc channel address msb 4 bits is a ) 4 r/w ddc write status (for external ddc access only) it is cleared after write. 3 r/w ddc sram write enable (for external ddc access only) 0: disable 1: enable 2 r/w ddc de-bounce enable 0: disable 1: enable (with crystal/4) 1 r/w ddc channel ram size 0: 128 bytes 1: 256 bytes 0 r/w ddc channel enable bit 0: mcu access enable 1: ddc channel enable address: fb ddc_index (ddc sram r/w index register) bit mode function 7:0 r/w ddc sram read/write index register [7:0] the ddc channel index register will be auto increased one by one after each read or write cycle. address: fc ddc_access_port (ddc channel access port) bit mode function 7:0 r/w ddc sram read/write port ** the ddc function can still work when power_down & power_save. ** after reset, the register will be set to default value, but the sram will keep original data. address: fd ddc_dvi_enable (ddc channel enable register) default: 00h bit mode function 7:5 r/w dvi ddc channel address least significant 3 bits (the default ddc channel address msb 4 bits is a ) 4 r dvi ddc external write status (for external ddc access only) it is cleared after write. 3 r/w dvi ddc external write enable (for external ddc access only) 0: disable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 160 1: enable 2 r/w dvi ddc debounce enable 0: disable 1: enable (with crystal/4) 1 r/w dvi ddc channel ram size 0: 128 bytes 1: 256 bytes 0 r/w dvi ddc channel enable switch 0: mcu access enable 1: external ddc access enable address: fe ddc_dvi_index (ddc sram r/w index register) bit mode function 7:0 r/w dvi ddc sram read/write index register [7:0] l the ddc channel index register will be auto increased one by one after each read or write cycle. address: ff ddc_dvi_access_port (ddc channel access port) bit mode function 7:0 r/w dvi ddc sram read/write port l the ddc function can still work when power_down & power_save. l after reset, the register will be set to default value, but the sram will keep original data. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 161 embedded osd addressing and accessing register address bit 7 6 5 4 3 2 1 0 high byte a15 a14 a13 a12 a11 a10 a9 a8 low byte a7 a6 a5 a4 a3 a2 a1 a0 figure 18. addressing and accessing registers date bit byte 0 d7 d6 d5 d4 d3 d2 d1 d0 byte 1 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 d7 d6 d5 d4 d3 d2 d1 d0 figure 2. data registers all kind of registers can be controlled and accessed by these 2 bytes, and each address contains 3-byte data, details are described as follows: write mode : [a15:a14] select which byte to write -00: byte 0 -01:byte 1 -10: byte 2 C 11: all *all data are sorted by these three bytes (byte0~byte2) [a13] auto load (double buffer) [a12] address indicator - 0: window and frame control registers. -1: font select and font map sram [a11:a0] address mapping - font select and font map sram address: 000~eff 3.75k*3byte -frame control register address: 000~0xx (latch) -window control register address: 100~1xx (latch) * selection of sram address or latch address selection is determined by a12! http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 162 example: bit [15:14]=00 -all data followed are written to byte0 and address increases. byte0 byte0 byte0 (address will auto increase) bit [15:14] =01 -all data followed are written to byte1 and address increases. byte1 byte1 byte1 (address will auto increase) bit [15:14] =11 - address will be increased after each 3-byte data written. byte0 byte1 byte2 byte0 byte1 byte2 (address will auto increase) window control registers l windows all support shadow/border/3d button l window0, 5, 6, 7 support gradient functions. l window 4, 5, 6, 7 start/end resolution are 1line(pixel), window 0, 1, 2, 3 start/end resolution are 4line(pixel), l all window start and end position include the special effect (border/shadow/3d button) been assigned l font comes after windows by 10 pixels, so you should compensate 10 pixels on windows to meet font position window 0 shadow/border/gradient address: 100h byte 0 bit mode function 7:6 -- reserved 5:3 w window 0 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 0 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness byte 1 bit mode function 7:4 w window 0 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border color 3:0 w window 0 border color index in 16-color lut http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 163 for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 164 window 0 start position address: 101h byte 0 bit mode function 7:2 w window 0 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 0 vertical start [2:0] line 4:0 w window 0 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 0 vertical start [10:3] line start position must be increments of four. window 0 end position address: 102h byte 0 bit mode function 7:2 w window 0 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 0 vertical end [2:0] line 4:0 w window 0 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 0 vertical end [10:3] line l end position must be increments of four. window 0 control address: 103h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 165 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 0 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 0 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 0 enable 0: disable 1: enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 166 window 1 shadow/border/gradient address: 104h byte 0 bit mode function 7:6 w reserved 5:3 w window 1 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 1 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness byte 1 bit mode function 7:4 w window 1 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border color 3:0 w window 1 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7:0 w reserved window 1 start position address: 105h byte 0 bit mode function 7:2 w window 1 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 1 vertical start [2:0] line 4:0 w window 1 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 1 vertical start [10:3] line start position must be increments of four. window 1 end position address: 106h http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 167 byte 0 bit mode function 7:2 w window 1 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 1 vertical end [2:0] line 4:0 w window 1 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 1 vertical end [10:3] line end position must be increments of four. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 168 window 1 control address: 107h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 1 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 1 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 1 enable 0: disable 1: enable window 2 shadow/border/gradient address: 108h byte 0 bit mode function 7:6 w reserved 5:3 w window 2 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 2 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 169 byte 1 bit mode function 7:4 w window 2 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border color 3:0 w window 2 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7:0 w reserved window 2 start position address: 109h byte 0 bit mode function 7:2 w window 2 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 2 vertical start [2:0] line 4:0 w window 2 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 2 vertical start [10:3] line start position must be increments of four. window 2 end position address: 10ah byte 0 bit mode function 7:2 w window 2 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 2 vertical end [2:0] line 4:0 w window 2 horizontal end [10:6] pixel byte 2 bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 170 7:0 w window 2 vertical end [10:3] line end position must be increments of four. window 2 control address: 10bh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 2 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 2 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 2 enable 0: disable 1: enable window 3 shadow/border/gradient address: 10ch byte 0 bit mode function 7:6 w reserved 5:3 w window 3 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 3 shadow/border height in line unit http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 171 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness byte 1 bit mode function 7:4 w window 3 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border color 3:0 w window 3 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7:0 w reserved window 3 start position address: 10dh byte 0 bit mode function 7:2 w window 3 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 3 vertical start [2:0] line 4:0 w window 3 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 3 vertical start [10:3] line start position must be increments of four. window 3 end position address: 10eh byte 0 bit mode function 7:2 w window 3 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 3 vertical end [2:0] line 4:0 w window 3 horizontal end [10:6] pixel http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 172 byte 2 bit mode function 7:0 w window 3 vertical end [10:3] line end position must be increments of four. window 3 control address: 10fh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 3 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 3 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 3 enable 0: disable 1: enable window 4 shadow/border/gradient address: 110h byte 0 bit mode function 7:6 w reserved 5:3 w window 4 shadow/border width or 3d button thickness in pixel unit http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 173 000~111: 1 ~ 8 pixel 2:0 w window 4 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness byte 1 bit mode function 7:4 w window 4 shadow color index in 16-color lut for 3d window, it is the left-top/ bottom border color 3:0 w window 4 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7:0 w reserved window 4 start position address: 111h byte 0 bit mode function 7:2 w window 4 horizontal start [5:0] 2:0 -- reserved byte 1 bit mode function 7:5 w window 4 vertical start [2:0] line 4:0 w window 4 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 4 vertical start [10:3] line window 4 end position address: 112h byte 0 bit mode function 7:2 w window 4 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 4 vertical end [2:0] line 4:0 w window 4 horizontal end [10:6] pixel http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 174 byte 2 bit mode function 7:0 w window 4 vertical end [10:3] line window 4 control address: 113h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7:4 -- reserved 3:0 w window 4 color index in 16-color lut byte 2 default: 00h bit mode function 7:5 w reserved 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 4 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 4 enable 0: disable 1: enable window 5 shadow/border/gradient address: 114h byte 0 bit mode function 7:6 w reserved 5:3 w window 5 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 175 2:0 w window 5 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness byte 1 bit mode function 7:4 w window 5 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border color 3:0 w window 5 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient window 5 start position address: 115h byte 0 bit mode function 7:2 w window 5 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 176 7:5 w window 5 vertical start [2:0] line 4:0 w window 5 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 5 vertical start [10:3] line window 5 end position address: 116h byte 0 bit mode function 7:2 w window 5 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 5 vertical end [2:0] line 4:0 w window 5 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 5 vertical end [10:3] line window 5 control address: 117h byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 5 color index in 16-color lut http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 177 byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 5 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 5 enable 0: disable 1: enable window 6 shadow/border/gradient address: 118h byte 0 bit mode function 7:6 w reserved 5:3 w window 6 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 6 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness ps: this is for non-rotary, rotate 270, rotate 90 and 180. byte 1 bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 178 7:4 w window 6 shadow color index in 16-color lut for 3d window, it is the left-top/ bottom border color 3:0 w window 6 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function 7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient window 6 start position address: 119h byte 0 bit mode function 7:2 w window 6 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 6 vertical start [2:0] line 4:0 w window 6 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 6 vertical start [10:3] line http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 179 window 6 end position address: 11ah byte 0 bit mode function 7:2 w window 6 horizontal end [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 6 vertical end [2:0] line 4:0 w window 6 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 6 vertical end [10:3] line window 6 control address: 11bh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 6 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 180 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 6 type 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 6 enable 0: disable 1: enable window 7 shadow/border/gradient address: 11ch byte 0 bit mode function 7:6 w reserved 5:3 w window 7 shadow/border width or 3d button thickness in pixel unit 000~111: 1 ~ 8 pixel 2:0 w window 7 shadow/border height in line unit 000~111: 1 ~ 8 line it must be the same as bit[5:3] for 3d button thickness ps: this is for non-rotary, rotate 270, rotate 90 and 180. byte 1 bit mode function 7:4 w window 7 shadow color index in 16-color lut for 3d window, it is the left-top/bottom border color 3:0 w window 7 border color index in 16-color lut for 3d window, it is the right-bottom/top border color byte 2 bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 181 7 w r gradient polarity 0: decrease 1: increase 6 w g gradient polarity 0: decrease 1: increase 5 w b gradient polarity 0: decrease 1: increase 4:3 w gradient level 00: 1 step per level 01: repeat 2 step per level 10: repeat 3 step per level 11: repeat 4 step per level 2 w enable red color gradient 1 w enable green color gradient 0 w enable blue color gradient window 7 start position address: 11dh byte 0 bit mode function 7:2 w window 7 horizontal start [5:0] 1:0 -- reserved byte 1 bit mode function 7:5 w window 7 vertical start [2:0] line 4:0 w window 7 horizontal start [10:6] pixel byte 2 bit mode function 7:0 w window 7 vertical start [10:3] line window 7 end position address: 11eh byte 0 bit mode function 7:2 w window 7 horizontal end [5:0] 1:0 -- reserved byte 1 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 182 bit mode function 7:5 w window 7 vertical end [2:0] line 4:0 w window 7 horizontal end [10:6] pixel byte 2 bit mode function 7:0 w window 7 vertical end [10:3] line window 7 control address: 11fh byte 0 bit mode function 7:0 -- reserved byte 1 bit mode function 7 -- reserved 6:4 w 111: 7 level per gradient 110: 6 level per gradient 101: 5 level per gradient 100: 4 level per gradient 011: 3 level per gradient 010: 2 level per gradient 001: 1 level per gradient 000: 8 level per gradient 3:0 w window 7 color index in 16-color lut byte 2 default: 00h bit mode function 7 w reserved 6 w gradient function 0: disable 1: enable 5 w gradient direction 0: horizontal 1: vertical 4 w shadow/border/3d button 0: disable 1: enable 3:1 w window 7 type http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 183 000: shadow type 1 001: shadow type 2 010: shadow type3 011: shadow type 4 100: 3d button type 1 101: 3d button type 2 110: reserved 111: border 0 w window 7 enable 0: disable 1: enable http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 184 3d button type 1 3d button type 2 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 185 type 1type 2type 3type 4 width height shadow in all direction osd appear range transparent start end window mask fade/in out function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 186 frame control registers address: 000h byte 0 bit mode function 7:0 r/w vertical delay [10:3] the bits define the vertical starting address. total 2048 step unit: 1 line vertical delay minimum should set 1 byte 1 bit mode function 7:0 r/w horizontal delay [9:2] the bits define the horizontal starting address. total 1024 step unit:4 pixels horizontal delay minimum should set 2 byte 2 default: xxxx_xxx0b bit mode function 7:6 r/w horizontal delay bit [1:0] 5:3 r/w vertical delay [2:0] 2:1 r/w display zone, for smaller character width 00: middle 01: left 10: right 11: reserved 0 r/w osd enable 0: osd circuit is inactivated 1: osd circuit is activated when osd is disabled, double width (address 0x002 byte1[1]) must be disabled to save power. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 187 pwm duty width address: 001h byte 0 default: 00h bit mode function 7:0 r/w pwm_0 8bits decides the output duty width and waveform of pwm at pwm channel byte 1 default: 00h bit mode function 7:0 r/w pwm_1 8bits decides the output duty width and waveform of pwm at pwm channel byte 2 default: 00h bit mode function 7:0 r/w pwm_2 8bits decides the output duty width and waveform of pwm at pwm channel address: 002h byte 0 default: 00h bit mode function 7:0 r/w first stage clock divider n[7:0] n=0-255, 1 st f= f/2(n+1) byte 1 default: 00h bit mode function 7 r/w pwm0 first stage clock divider enable 0: disable 1: enable 6 r/w pwm1 first stage clock divider enable 0: disable 1: enable 5 r/w pwm2 first stage clock divider enable 0: disable 1: enable 4 r/w enable pwm output 3:2 r/w crystal clock divider 00: crystal 01: crystal/2 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 188 10: crystal/4 11: crystal/8 1:0 -- reserved byte 2 default: 00h bit mode function 7:0 -- reserved address: 003h byte 0 default: 00h bit mode function 7 r/w specific color blending (blending type 2) 0: disable 1: enable 6:5 r/w window 7special function 00: disable 01: blending (blending type 3) 10: window 7 mask region appear 11: window 7 mask region transparent 4 r/w osd vertical start input signal source select 0: select dvs as osd vsync input 1: select ena as osd vsync input 3:0 r/w blending color from 16-color lut (blending type 2) byte 1 bit mode function 7:4 r/w char shadow/border color 3: 2 r/w alpha blending type (blending type 1) 00: disable alpha blending 01: only window blending 10: all blending 11: window and character background blending 1 r/w double width enable (for all osd including windows and characters) 0: normal 1: double 0 r/w double height enable (for all osd including windows and characters) 0: normal 1: double total blending area = blending type1 area + blending type 2 area + blending type 3 area http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 189 byte 2 bit mode function 7:6 r/w font downloaded swap control 0x: no swap 10: ccw 11: cw 5:2 -- reserved 1 r/w global blinking enable 0: disable 1: enable 0 r/w rotation 0: normal (data latch 24 bit per 24 bit) 1: rotation (data latch 18 bit per 24 bit) bit 7 6 5 4 3 2 1 0 firmware a b c d e f g h cw a e b f c g d h ccw e a f b g c h d http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 190 figure 3 non-rotated memory alignments 23 6 figure 4 rotated memory alignments base address offset address: 004h byte 0 bit mode function 7:0 r/w font select base address[7:0] byte 1 bit mode function 7:4 r/w font select base address[11:8] 3:0 r/w font base address[3:0] byte 2 bit mode function 7:0 r/w font base address[11:4] 23~12 bit(high) 11~0 bit(low) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 191 osd compression address: 005h byte 0 bit mode function 7:4 r/w 4-bit value for vlc code 0 3:0 r/w 4-bit value for vlc code 100 byte 1 bit mode function 7:4 r/w 4-bit value for vlc code 1010 3:0 r/w 4-bit value for vlc code 1011 byte 2 bit mode function 7:4 r/w 4-bit value for vlc code 1100 3:0 r/w 4-bit value for vlc code 1101 0 address: 006h byte 0 bit mode function 7:4 r/w 4-bit value for vlc code 1101 1 3:0 r/w 4-bit value for vlc code 1110 0 byte 1 bit mode function 7:4 r/w 4-bit value for vlc code 1110 10 3:0 r/w 4-bit value for vlc code 1110 11 byte 2 bit mode function 7:4 r/w 4-bit value for vlc code 1111 00 3:0 r/w 4-bit value for vlc code 1111 01 address: 007h byte 0 bit mode function 7:4 r/w 4-bit value for vlc code 1111 100 3:0 r/w 4-bit value for vlc code 1111 101 byte 1 bit mode function http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 192 7:4 r/w 4-bit value for vlc code 1111 110 3:0 r/w 4-bit value for vlc code 1111 1110 byte 2 default: xxxx_xxx0b bit mode function 7:1 -- reserved 0 r/w osd compression (4bit/symbol, vlc code 1111_1111 represents the end of data) (only for sram) 0: disable 1: enable note: 1. if enable osd compression or auto load (double buffer), only one byte can be read after writing address at 0x90, 0x91. 2. for osd compression, msb 4 bits of original byte is first transferred to corresponding vlc code, and then lsb 4 bits is transf+erred. vlc code is placed from lsb to msb of compression font. for example, 4-bit value for vlc code 1100 is 4 b0101, and 4-bit value for vlc code 100 is 4 b0001. original data 0x15 is transferred to compression x0011001. 3. osd double buffer and compression can t be enabled simultaneous. 4. when power-down mode or lack of crystal clock, osd compression font can t be write. 5. after osd enable, it is better to delay 1 dvs to start writing osd compression data. osd sram (map and font registers) r0 r1 r2 . rn end c01 c02 b03 c04 c11 c12 c13 cn1 cn2 1-bit font start 2-bit font start 4-bit font start 11.25k bytes sram 1. row command http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 193 r0 r1 r2 r3 r . rn end row command r0~rn represent the start of new row. each command contains 3 bytes data which define the length of a row and other attributes. osd end command represent the end of osd. r0 is set in address 0 of sram. 2. character/blank command (font select) character command is used to select which character font is show. each command contains three bytes which specify its attribute and 1,2 or 4bit per pixel. blank command represents blank pixel to separate the preceding character and following character. use two or more blank command if the character distance exceeds 255 pixel. the font select base address in frame control register represents the address of the first character in row 0, that is, c01 in the above figure. the following character/blank is write in the next address. c11 represents the first character in row1, c12 represents the second character in row1, and so on. the address of the first character cn1 in row n = font select base address + row 0 font base length + row 1 font base length + +row n-1 font base length. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 194 3. font user fonts are stored as bit map data. for normal font, one font has 12x18 pixel, and for rotation font, one has 18x12 pixel. one pixel use 1, 2 or 4 bits. for 12x18 font, one 1-bit font requires 9 * 24bit sram one 2-bit font requires 18 * 24bit sram one 4-bit font requires 36 * 24bit sram for 18x12 font, one 1-bit font requires 12 * 24bit sram one 2-bit font requires 24 * 24bit sram one 4-bit font requires 48 * 24bit sram font base address in frame control register point to the start of 1-bit font. for normal (12x18) font: 1-bit font, if cs = 128, real address of font = font base address + 9 * 128 2-bit font, if cs = 128, real address of font = font base address + 18 * 128 4-bit font, if cs = 128, real address of font = font base address + 36 * 128 for rotational (18x12) font: 1-bit font, if cs = 128, real address of font = font base address + 12 * 128 2-bit font, if cs = 128, real address of font = font base address + 24 * 128 4-bit font, if cs = 128, real address of font = font base address + 48 * 128 where cs is character selector in character command. note that row command, font select and font share the same osd sram. when we download the font, we have to set the frame control 002h byte1 [1:0] to set the method of hardware bit swap. if the osd is counter-clock-wise rotated, we have to set to 0x01 (the 8 bits of every byte of font sram downloaded by firmware will be in a sequence of 7 5 3 1 6 4 2 0 (from msb to lsb) and should be rearranged to 7 6 5 4 3 2 1 0 by hardware). if it is clock-wise rotated, we have to set to 0x10 (the 8 bits of every byte of font sram downloaded by firmware will be in a sequence of 6 4 2 0 7 5 3 1 (from msb to lsb) and should be rearranged to 7 6 5 4 3 2 1 0 by hardware). after we finish the downloading or if we don t have to rotate the osd, we have to set it to 0x00 . http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 195 row command byte 0 bit mode function 7 w 1: row start command 0: osd end command each row must start with row-command, last word of osd map must be end-command 6:5 w reserved 4:2 w character border/shadow 000: none 001: border 100: shadow (left-top) 101: shadow (left-bottom) 110: shadow (right-top) 111: shadow (right-bottom) 1 w double character width 0: x1 1: x2 0 w double character height 0: x1 1: x2 byte 1 bit mode function 7:3 w row height (1~32) 2:0 w column space 0~7 pixel column space when char is doubled, so is column space. notice: when character height/width is doubled, the row height/column space definition also twice. if the row height is larger than character height, the effect is just like space between rows. if it is smaller than character height, it will drop last several bottom line of character. when using 1/2/4lut font, column space and font smaller than row height, the color of column space and row space is the same as font background color, only 4 bit true color font mode, the color is transparent http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 196 12 25 a 1/2/4lut bg color the same as character background ,4 true color mode, bg color is transparent row space color column space color byte 2 bit mode function 7:0 w row length unit: font base character command (for blank) byte 0 bit mode function 7 w 0 6 w blinking effect 0: disable 1: enable 5:0 w reserved byte 1 bit mode function 7:0 w blank pixel length at least 3 pixels, and can t exceed 255 pixels. byte 2 bit mode function 7:5 w reserved 4 w reserved 3:0 w blank color C select one of 16-color lut (0 is special for transparent) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 197 character command (for 1-bit ram font) byte 0 bit mode function 7 w 1 6 w character blinking effect 0: disable 1: enable 5:4 w 00 (font type 00: 1-bit ram font 01: 4-bit ram font 1x: 2-bit ram font) 3:0 w character width (only for 1-pixel font, doubled when specifying double-width in row/blank command register) for 12x18 font: 0100: 4-pixel 0101: 5-pixel 0110: 6-pixel 0111: 7-pixel 1000: 8-pixel 1001: 9-pixel 1010: 10-pixel 1011:11-pixel 1100: 12-pixel for 18x12 font (rotated) 0000: 4-pixel 0001: 5-pixel 0010: 6-pixel 0011: 7-pixel 0100: 8-pixel 0101: 9-pixel 0110: 10-pixel 0111: 11-pixel 1000: 12-pixel 1001:13-pixel 1010:14-pixel 1011:15-pixel 1100: 16-pixel 1101:17-pixel 1110:18-pixel when using border/shadow/ effect, the width of the 1-bit font should at least 6 pixel. byte 1 bit mode function 7:0 w character select [7:0] byte 2 bit mode function 7:4 w foreground color select one of 16-color from color lut 3:0 w background color select one of 16-color from color lut (0 is special for transparent) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 198 character command (for 2-bit ram font) byte 0 bit mode function 7 w 1 6 w msb of foreground color 11, background 00 5 w 1 4 w msb of foreground color 10, foreground 01 3:1 w foreground color 11 select one of 8 color from color lut add byte0 [6] as msb for 16-color lut. 0 w background color 00 bit[2] select one of 8 color from color lut byte 1 bit mode function 7:0 w character select [7:0] byte 2 bit mode function 7:6 w background color 00 bit[1:0] select one of 8 color from color lut while 0 is special for transparent add byte0 [6] as msb for 16-color lut. once we fill 0000 or 1000(msb follow byte0[6]), bg appears transparent. 5:3 w foreground color 10 select one of 8 color from color lut add byte0 [4] as msb for 16-color lut. 2:0 w foreground color 01 select one of 8 color from color lut add byte0 [4] as msb for 16-color lut. character command (for 4-bit ram font) byte 0 bit mode function 7 w 1 6 w character blinking effect 0: disable 1: enable 5:4 w 01 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 199 (font type 00: 1-bit ram font 01: 4-bit ram font 1x: 2-bit ram font) 3:0 w (for byte1[7] = 0) select one color from 16-color lut as background (for byte1[7] = 1) red color level msb 4 bits for 8 bits color level (lsb 4 bits are 1111) byte 1 bit mode function 7 w 0: 4bit look up table, 0000 b is transparent. 1: 3bit specify r,g,b pattern, color level defined in byte0[3:0],byte2. one mask bit defines foreground or background. 6:0 w character select [6:0] l when 4-bit look-up table mode color of column space is the same as background. l when 4-bit look-up table mode and pixel value is 0000, and byte0[3:0]=0000 means transparent. l when true color mode and pixel value is 0000 it is transparent byte 2 bit mode function 7:4 w (for byte1[7] = 1) green color level msb 4 bits for 8 bits color level (lsb 4 bits are 1111) 3:0 w (for byte1[7] = 1) blue color level msb 4 bits for 8 bits color level (lsb 4 bits are 1111) http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 200 t window 0 window 1 window 2 window 3 window 4 window 5 a window 7 window 6 display priority we have four windows with gradient and four windows without gradient, the window priority is as above, character should be always on the top layer of the window. pattern gen. use osd to replace display pattern generator. chess board : make a font as below if we want to fill to the full 1280x1024 screen with character, we need 1280*1024 pixels. required character is: using 12*18 font 1280/12 = 106.7 -> 107 1024/18 = 56.9 -> 57 107*57 = 6099 character http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 201 the required number of character map is larger than ram size. we must turn on double width or double height function to reduce the half of character map. so the basic unit to chessboard is 2x2 pixel. you can use larger chessboard instead of 2x2 pixels unit, such as 4x4 and so on. gray level we can display 256 gray level by gradient window, 8 and 16 gray level by character map. 32 and 64 gray level is not supported. http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 202 http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 203 5.electric specification dc characteristics table 2 absolute maximum ratings parameter symbol min typ max units voltage on input (5v tolerant) v in -1 5 v electrostatic discharge v esd 2.5 kv latch-up i la 100 ma ambient operating temperature t a 0 70 o c storage temperature (plastic) t stg -55 125 o c thermal resistance (junction to air) ja 38 o c/w table 3 dc characteristics/operating condition (0 < ta < 70 ; vdd = 3.3v 0.3v) parameter symbol min typ max units supply voltage vdd 3.0 3.3 3.6 v supply current(all function on at 135m) digital supply dclk pll supply mclk pll supply i vdd i dvcc i avcc i pvcc ma supply current(power saving) digital supply dclk pll supply mclk pll supply i vdd i dvcc i avcc i pvcc ma output high voltage v oh 2.4 vdd v output low voltage v ol gnd 0.5 v input high voltage v ih 2.0 v input low voltage v il 0.8 v i/o pull-up resistance r pu 100 300 i/o pull-down resistance r pd 50 150 input leakage current(vi=vcc or gnd) i li -10 +10 a output leakage current(vo=vcc or gnd) i lo -20 +20 a http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 204 6. mechanical specification 128 pin package http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 205 note: symbol dimension in inch dimension in mm 1.dimension d & e do not include interlead min type max min type max flash. a 2.dimension b does not include dambar a 1 0.004 0.010 0.036 0.10 0.25 0.91 protrusion/intrusion. a 2 0.102 0.112 0.122 2.60 2.85 3.10 3.controlling dimension: millimeter b 0.005 0.009 0.013 0.12 0.22 0.32 4.general appearance spec. should be based c 0.002 0.006 0.010 0.05 0.15 0.25 on final visual inspection spec. d 0.541 0.551 0.561 13.75 14.00 14.25 title : 128ld qfp ( 14x20 mm*2 ) package outline e 0.778 0.787 0.797 19.75 20.00 20.25 - cu l/f, footprint 3.2 mm e 0.010 0.020 0.030 0.25 0.5 0.75 leadframe material: h d 0.665 0.677 0.689 16.90 17.20 17.50 approve doc. no. 530-ass-p004 h e 0.902 0.913 0.925 22.90 23.20 23.50 version 1 l 0.027 0.035 0.043 0.68 0.88 1.08 page of l 1 0.053 0.063 0.073 1.35 1.60 1.85 check dwg no. q128 - 1 y 0 realtek semi- conductor co., ltd http://www..net/ datasheet pdf - http://www..net/
realtek RTD2553V series 206 7. ordering information the available RTD2553V series pin compatible products listed below: part number adc dvi hdcp resolution output package RTD2553V 210mhz ( 2 ports) yes no wuxga/uxga/ws xga+ lvds/rsds/ttl 128 qfp rtd2533v 165mhz (2 ports) yes no sxga/wxga+ lvds/rsds/ttl 128 qfp rtd2033v 165mhz (2 ports) no no sxga/wxga+ lvds/rsds/ttl 128 qfp RTD2553Vh 210mhz ( 2 ports) yes yes wuxga/uxga/ws xga+ lvds/rsds/ttl 128 qfp rtd2533vh 165mhz (2 ports) yes yes sxga/wxga+ lvds/rsds/ttl 128 qfp RTD2553V-lf 210mhz ( 2 ports) yes no wuxga/uxga/ws xga+ lvds/rsds/ttl 128 qfp (lead free) rtd2533v-lf 165mhz (2 ports) yes no sxga/wxga+ lvds/rsds/ttl 128 qfp (lead free) rtd2033v-lf 165mhz (2 ports) no no sxga/wxga+ lvds/rsds/ttl 128 qfp (lead free) RTD2553Vh-lf 210mhz ( 2 ports) yes yes wuxga/uxga/ws xga+ lvds/rsds/ttl 128 qfp (lead free) rtd2533vh-lf 165mhz (2 ports) yes yes sxga/wxga+ lvds/rsds/ttl 128 qfp (lead free) * lead free packages are available for above items with suffix C lf. http://www..net/ datasheet pdf - http://www..net/

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